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vs_fftw3

可在VS下编译的fftw3

vscode-verilog-hdl-support

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

vscode-vlang

V Language extension for Visual Studio Code.

vsdbabysoc

VSDBabySoC is a small SoC including PLL, DAC and a RISCV-based processor named RVMYTH.

vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

vsdfpga

Implementation of Mixed Signal SoC (RISCV based Core + PLL) on FPGA

vsensor

虚拟传感器

vsf-tinyembededsoftware

Versaloon Software Framework -- a tiny preemptive-capable event-driven incremental software framework for embedded systems

vsl

A pure-V scientific library with a great variety of functions.

vslam

Basic algorithms for vslam.

vslam-1

vslam

vslam-2

开源SLAM方案学习过程记录

vsx-agent

manager of client transactions with distance calculation acceleration hardware

vsx-board

manufacturing and design files for VSX and its service card

vsx-client

Client interface for requesting hardware accelerated distance calculation

vsx-core-agent-coprocessor-fpga

host to DCEs agent RTL for xc7a75tfgg676-2

vsx-core-dce-coprocess-engine

VSX distance calculation engine RTL for lfe5u-85f-8bg381i

vta_systemc

SystemC implementation of VTA accelerator

vtbl-ida-pro-plugin

Identifying Virtual Table Functions using VTBL IDA Pro Plugin + Deviare Hooking Engine

vtec_calculator

After parsing the RINEX file, the Vertical Total Electron Content is calculated.

vtl

The V Tensor Library

vtol

大创项目-垂直起降转平飞无人机

vtol-system-identification

vtol_mw

尾座式垂直起降无人机

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

vulcan2

vulkan-particles

Simple vulkan particles example

vulkan.jl

Simplify usage of Vulkan in Julia

vulkanmemoryallocator

Easy to integrate Vulkan memory allocation library

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog