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risc-v-chisel-project

This is a starter template for your custom RISC-V project. It will allow you to leverage the Chisel HDL and RocketChip SoC generator to produce a RISC-V SoC with MMIO-mapped peripherals, DMA, and custom accelerators.

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

risc-v-cpu-with-tlv

Building a RISC-V CPU Core using TLV in makerchip.com

risc-v-cryptographic-coprocessor

risc-v-fault-detector

Merging the AXIs of the three RISC-V cores and detect incoherencies. If an incoherency is detected, the faulty core is reseted to the correct state.

risc-v-fyp

The purpose of this final year project (FYP) is to design and implement a 5-stage pipelined RISC-V processor in VHDL as an education tool.

risc-v-implementation

This is a Verilog Implementation of RISC-V CPU that implements RV32I and RV16I and supports interrupt handling and some CSR instuctions and registers

risc-v-multicore

An implementation of a RISC V multicore processor targeting FPGAs.

risc-v-on-pynq

RISC-V Integration for PYNQ

risc-v-otter

RISC-V hardware implementation using Verilog

risc-v-out-of-order-processor

A simple 9 instruction 2-issue RISC-V Out of Order Processor designed for UCLA's M116C Computer Architecture

risc-v-processor

risc-v-python-verilog-microcontroller

risc-v-registers-router

Outsourcing and merging the routers of the RISC-V cores for reset

risc-v-single-cycle-core-logisim

RV32I single cycle simulation on an open-source software Logisim.

risc-v-sympl-hybrid-floating-point-isa-compute-engine

New hybrid ISA genetically splices the instruction pipeline of a RISC-V to the instruction pipelines of one or more SYMPL Compute Engines, giving you the best of both worlds in a single package.

risc-v-tensorcore

Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra

risc-v-tlm

RISC-V SystemC-TLM simulator

risc-v-vector

Vector processor for RISC-V vector ISA

risc-v-vector-hardware

risc-v-vector-processor

256-bit vector processor based on the RISC-V vector (V) extension

risc-v_core_external_sram_imem

risc-v_core_on_fpga

risc-v_myth_workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

risc-v_processors

risc-v_vector_accelerator_for_ml

risc-v_xilinx-sdr-gnss

Repositório para fazer o port do RISC V para o xilinx. Ainda não decidido se será Kintex ou virtex.

risc-vec

A risc based process unit supporting vector

risc0

RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.

riscboy-ice40hx

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink