Microarchitecture implementation of the decoupled vector-fetch accelerator
Home Page: http://hwacha.org/
To use this co-processor, include this repo as a git submodule and add it as
to your chip's build.sbt as a Project, e.g.
lazy val hwacha = Project(file("hwacha"), "hwacha")
.settings(buildSettings)
.dependsOn(rocketchip)
Hwacha depends on the Rocket Chip project. Make sure the proper JARs are installed. For more information on how to use this co-processor, refer to (https://github.com/ucb-bar/chipyard).
1.Does Hwacha support GDB for debugging？
2.Use“spike -H --rbb-port=9824 --extension=hwacha vec-vvadd.riscv”，this program doesn‘t start halted，not allowing a debugger to connect。why？how to solve the problem for debugging Hwacha instructions？
I notice that VRU support is removed 5/22/2017 by Colin with the comments "TODO: Fix prefetcher using TL2 Hints"
Is there any plan on bringing VRU back?
BTW, what will happen if the submit in 5/22/2017 is reverted? Any bug in VRU?
Best Regard,
Roy
Hello,
I am currently optimizing a code to run using Hwacha and I have this scenario.
for(int i = 0; i < n; i++){
out[i] = vec1[i]* const_float / vec2[i] + const_float2;
}
So I know I can do the vector division on Hwacha, but it would be nice to have an operation to perform the multiplication by scalar and and operation like SAXPY but with divide. For example, SADPY so that I could do the following:
mul_scalar_vec_hwacha(out, vec1, const_float)
sadpy(out, vec2, const_float2)
Is there any instruction on the ISA to perform this? I have been looking for it but I can't find any.
Thanks in advance!
As in the subject, is there a exist way to track the hardware usage cycle by cyle in FPGA?
Say can we trace the hardware usage and write the result into the memory?
how to specify the number of shared units (for example the FMA units) in a lane?
@jerryz123 is trying to port some BLAS-like stuff to Hwacha and he's found that it asserts when running any code. He's running HwachaConfig. By commenting out assertions he was able to get it to run the ASM tests.
diff --git a/src/main/scala/lane.scala b/src/main/scala/lane.scala
index 8014aef..b9e51a2 100644
--- a/src/main/scala/lane.scala
+++ b/src/main/scala/lane.scala
@@ -181,7 +181,7 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
require(n <= uop.bits.nOperands)
(0 until n) map { i =>
val ri = rbase+i
- assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)
+ // assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)
Mux(uop.bits.sreg(i), splat_scalar(ctrl.io.uop.sreg(ri).bits), opls(ri))
}
}
@@ -208,9 +208,9 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
io.lrqs(1).valid := ctrl.io.uop.vqu.valid && ctrl.io.uop.vqu.bits.fn.latch(1) && vqu_pred.active()
io.lrqs(1).bits.data := vqu_operands(1)
- assert(!io.lpqs(0).valid || io.lpqs(0).ready, "check lpqs(0) counter logic")
- assert(!io.lrqs(0).valid || io.lrqs(0).ready, "check lrqs(0) counter logic")
- assert(!io.lrqs(1).valid || io.lrqs(1).ready, "check lrqs(1) counter logic")
+ //assert(!io.lpqs(0).valid || io.lpqs(0).ready, "check lpqs(0) counter logic")
+ //assert(!io.lrqs(0).valid || io.lrqs(0).ready, "check lrqs(0) counter logic")
+ //assert(!io.lrqs(1).valid || io.lrqs(1).ready, "check lrqs(1) counter logic")
val vgu_pred = predicate(3)
val vgu_operands = operands("vgu", ctrl.io.uop.vgu, 1, 5)
@@ -219,8 +219,8 @@ class Lane(implicit p: Parameters) extends VXUModule()(p) with Packing with Rate
io.lrqs(2).valid := ctrl.io.uop.vgu.valid && vgu_pred.active()
io.lrqs(2).bits.data := vgu_operands(0)
- assert(!io.lpqs(1).valid || io.lpqs(1).ready, "check lpqs(1) counter logic")
- assert(!io.lrqs(2).valid || io.lrqs(2).ready, "check lrqs(2) counter logic")
+ //assert(!io.lpqs(1).valid || io.lpqs(1).ready, "check lpqs(1) counter logic")
+ //assert(!io.lrqs(2).valid || io.lrqs(2).ready, "check lrqs(2) counter logic")
val vimu_pred = predicate(0)
val vimu_operands = operands("vimu", ctrl.io.uop.vimu, 2, 0)
diff --git a/hwacha b/hwacha
--- a/hwacha
+++ b/hwacha
@@ -1 +1 @@
-Subproject commit 9367d958cd2a917e2b9f2d8dc893e4e8517fa7ac
+Subproject commit 9367d958cd2a917e2b9f2d8dc893e4e8517fa7ac-dirty
diff --git a/project/build.scala b/project/build.scala
index 8004792..0ee8f52 100644
--- a/project/build.scala
+++ b/project/build.scala
@@ -20,7 +20,7 @@ object BuildSettings extends Build {
lazy val cde = project in file("context-dependent-environments")
lazy val hardfloat = project.dependsOn(chisel)
lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(chisel, cde, hardfloat)
-
+ lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings)
lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
val setMake = NotSpace ~ ( Space ~> NotSpace )
diff --git a/riscv-tools b/riscv-tools
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 1fca1bf57f227fa4e85cbdef0615873229d4d354
+Subproject commit 1fca1bf57f227fa4e85cbdef0615873229d4d354-dirty
diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 90f4871..909bb59 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -131,6 +131,8 @@ class DualBankConfig extends Config(
new WithNBanksPerMemChannel(2) ++ new BaseConfig)
class DualBankL2Config extends Config(
new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
+class QuadBankL2Config extends Config(
+ new WithNBanksPerMemChannel(4) ++ new WithL2Cache ++ new BaseConfig)
class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
class DualChannelL2Config extends Config(
diff --git a/src/main/scala/rocketchip/PrivateConfigs.scala b/src/main/scala/rocketchip/PrivateConfigs.scala
index 1c8a823..6e4b0cc 100644
--- a/src/main/scala/rocketchip/PrivateConfigs.scala
+++ b/src/main/scala/rocketchip/PrivateConfigs.scala
@@ -83,6 +83,25 @@ class ISCA2016Config extends Config(
}
}
+class ISCA2016Config1 extends Config(
+ new Process28nmConfig ++
+ new WithNMemoryChannels(1) ++ new WithNBanksPerMemChannel(4) ++
+ new WithNL2AcquireXacts(4) ++ new WithL2Capacity(256) ++ new With32BtbEntires ++ new HwachaConfig)
+{
+ override val knobValues:Any=>Any = {
+ case "HWACHA_NSRAMRF_ENTRIES" => 256
+ case "HWACHA_BUILD_VRU" => true
+ case x => (new Config(new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++ new WithL2Capacity(256) ++ new HwachaConfig)).knobValues(x)
+ }
+
+ override val topConstraints:List[ViewSym=>Ex[Boolean]] = {
+ List(
+ {ex => (ex(HwachaNSRAMRFEntries) === 256)},
+ {ex => (ex(HwachaBuildVRU) === true || ex(HwachaBuildVRU) === false)}
+ )
+ }
+}
+
class ISCA2016L2Config extends Config(new WithNLanes(2) ++ new ISCA2016Config)
class ISCA2016L4Config extends Config(new WithNLanes(4) ++ new ISCA2016Config)
diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala
index 26c60d9..5d44a04 100644
--- a/src/main/scala/uncore/tilelink2/Monitor.scala
+++ b/src/main/scala/uncore/tilelink2/Monitor.scala
@@ -35,7 +35,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
when (bundle.opcode === TLMessages.Get) {
assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), "'A' channel carries Get type unsupported by manager" + extra)
assert (source_ok, "'A' channel Get carries invalid source ID" + extra)
- assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
+ //assert (is_aligned, "'A' channel Get address not aligned to size" + extra)
assert (bundle.param === UInt(0), "'A' channel Get carries invalid param" + extra)
assert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
}
@@ -253,7 +253,7 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
when (bundle.opcode === TLMessages.AccessAckData) {
assert (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
- assert (is_aligned, "'D' channel AccessAckData address not aligned to size" + extra)
+ //assert (is_aligned, "'D' channel AccessAckData address not aligned to size" + extra)
assert (sink_ok, "'D' channel AccessAckData carries invalid sink ID" + extra)
// size is ignored
assert (bundle.param === UInt(0), "'D' channel AccessAckData carries invalid param" + extra)
Hwacha uses FPInput/FPResult in scalar-fpu-interface.scala, but io.cp_resp.valid never set to true, it is not connected to divSqrt_wen only to mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint. This means that all operations with div/sqrt always stall pipeline when we try to use boom with hwacha with scalar div/sqrt operations in hwacha i.e. rv64ud-p-svec-fdiv.
I was wondering if this project could be used to accelerate xtensor code. Would the compiler be able to auto-vectorize?
The website linked from this repository's About section seems unavailable now. Removing or updating the link to a UCB EECS tech report or whatever would be great.
I'm building hwacha with a lane number not in power of 2 and of course it failed.
So I'm wondering how I can modify the code to support a lane count not in power of 2?
What is the behavior for AMO instruction when vreg[rs1][i+1] is the same value with vreg[rs1][i] as in below pseudocode? Will vreg[vd][i+1] pick the updated value in memory?
for (int i=0; i<vl; ++i)
if ([!]preg[p][i])
atomic {
temp = mem[s1 ? vreg[rs1][i] : sreg[rs1]];
mem[s1 ? vreg[rs1][i] : sreg[rs1]] = amoop(temp, s2 ? vreg[rs2][i] : sreg[rs2]);
vreg[vd][i] = temp;
}
Actually AMO instruction cannot be run in hwacha template now. How can I verify AMO instruction in this stage?
Chipyard/dev found a bug in running asm tests with Hwacha on Rocket.
Should hwacha support scalar fdiv and fsqrt?
At now, when trying to execute these instructions, hwacha "hangs". This is because the FPU from Rocket does not form resp.valid. Instead, it forms nack_mem.
But nack_mem does not exist in rocc (and in hwacha logic).
Here it is in FPUIO:
So should hwacha work with these instructions?
I'm wondering whether Hwacha supporrts the RISC-V Vector extension.
Hi,
I'm running such a piece of code in hwacha
vset vp0
vpl vp1, va1
vlw vv1, va0
@vp1 vfirst vs1, vv1
...
It runs successfully in Spike, while gets the following assertion in hwacha
at scalar-unit.scala:297 assert(!vf_active || !io.imem.resp.valid || id_ctrl.ival, "illegal instruction exception!")
I looked into scalar-unit.scala and found that it seems there is no decode table for vpl/vps instructions.
Does these two instructions supported in hwacha?
Thanks,
-Shuyun
We wanted to start some research with the hwacha architecture.
Is RISC-V vector extensions support in the cards at this moment?
If yes, when do you plan to get to it?
If not, what is the rationale for hwacha to maintain a custom architecture?
Thanks in advance.
hi
we want to add an reduction instruction to sum all the element of a vector and the result is placed in a shared register.
You can see the similar instruction of vredsum.vs in the v-spec of risc-v and its web site is https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc.
I copy the example of the vredsum.vs instruction below.
vredsum.vs vd, vs2, vs1, vm # vd[0] = sum( vs2[*] , vs1[0] )
Could you please give us some advice how to implement it in hwacha? Thanks.
Best Regards,
--gao
Hi,
When we change the value of the parameter HwachaNVectorRegs and HwachaNSRAMRFEntries into 32, we found that the nvsreq and nvlreq in hwacha.scala are not satisfied and an error is reported as follows.
firrtl.passes.CheckWidths$BitsWidthException: @[dcc-mem.scala 613:33:[email protected]]: [module VLU] High bit 9 in bits operator is larger than input width 5 in bits(_T_1675, 9, 0).
firrtl.passes.PassException: 4 errors detected!
after we change the nvsreq and nvlreq as below, there is no error.
val nvsreq = math.max(p(HwachaNVectorRegs), p(HwachaNSRAMRFEntries)) * p(HwachaBankWidth) / p(HwachaRegLen)
val nvlreq = math.max(p(HwachaNVectorRegs), p(HwachaNSRAMRFEntries)) * p(HwachaBankWidth) / p(HwachaRegLen)
Could you please confirm whether the change for nvsreq and nvlreq is right? thanks.
--gao
currently WithConfPrec is set to off by default, so there is no difference between the HOV Configs and LOV Configs.
It seems that the ConfPrec can work now. maybe it can be reenabled now.
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