ricardoyx Goto Github PK

chisel3

Chisel 3: A Modern Hardware Design Language

computer-science-textbooks

Collect some CS textbooks for learning.

cs-notes

:books: 技术面试必备基础知识、Leetcode、计算机操作系统、计算机网络、系统设计、Java、Python、C++

e200_opensource

The Ultra-Low Power RISC Core

hello-world

Just guidence

helmet-detection

This project is a proof-of-concept, trying to show surveillance of roads for the safety of motorcycle and bicycle riders can be done with a surveillance camera and an onboard Jetson platform.

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

hwacha-template

Template for projects using the Hwacha data-parallel accelerator

lenet_cpp_remake

Simplified LeNet-5 with C++ based on x86 & RISC-V

libpku

北京大学课程资料整理

liuyanban

mips-32bit

Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

my-movies

use angular7 to build a weapp.

oscpu-framework

A Verilator-based demo.

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

plct-open-reports

PLCT实验室的公开演讲，或者决定公开的组内报告

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

ricardoyx.github.io

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

rv32

verilog RV32 cpu (CS3410)

tutorials

教程

ustc-cs-courses-resource

:heart:**科学技术大学计算机学院课程资源(https://mbinary.xyz/ustc-cs/)

vortex

vue_start

IT includes a vue2 webapp and a server writed by node.js

writing-your-first-riscv-simulator

《从零开始的RISC-V模拟器开发》配套的PPT和教学资料

xiangshan

Open-source high-performance RISC-V processor

zero-riscy

zero-riscy CPU Core