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axe

Consistency checker for memory subsystem traces

barstools

Useful utilities for BAR projects

berkeley-softfloat-3

SoftFloat release 3

berkeley-testfloat-3

TestFloat release 3

block-inclusivecache-sifive

boringssl

Mirror of BoringSSL

capstone

Mirror of git://qemu.org/capstone.git

chipyard

An Agile Chisel-Based SoC Design Framework

chipyard-toolchain-prebuilt

Pre-built riscv-gnu-toolchain binaries. You should most likely only shallow clone this.

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3: A Modern Hardware Design Language

coremark-workload

FireMarshal workload for CoreMark EEMBC

cryptography

cryptography is a package designed to expose cryptographic primitives and recipes to Python developers.

csi2rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

dramsim2

DRAMSim2: A cycle accurate DRAM simulator

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

dtc

Mirror of git.qemu.org/dtc.git

edk2

educational-materials

Educational materials for RISC-V

esp-gnu-toolchain

Custom extensions to the RISC-V toolchain for the UCB-BAR ESP project

esp-isa-sim

Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project

esp-tests

Custom extensions to the RISC-V tests for the UCB-BAR ESP project

firemarshal

Automatically Builds a Linux Distribution for FireSim/FireChip Nodes, works with FireSim's automatic workload generation.

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firrtl

Flexible Intermediate Representation for RTL

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

gdspy

Python module for creating GDSII stream files, usually CAD layouts.

gemmini

Berkeley's Systolic Array Generator

hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator