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airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

bithesis

📖 北京理工大学非官方 LaTeX 模板集合，包含本科、研究生毕业设计模板及更多。🎉 （更多文档请访问 wiki 和 release 中的手册）

clacc

Deep Learning Accelerator (Convolution Neural Networks)

cluster_interconnect

cnn-accelerator-vlsi

Convolutional accelerator kernel, target ASIC & FPGA

cnn-fpga

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

common_cells

Common SystemVerilog components

common_verification

SystemVerilog modules and classes commonly used for verification

convolution_network_on_fpga

CNN acceleration on virtex-7 FPGA with verilog HDL

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

e203_hbirdv2

The Ultra-Low Power RISC-V Core

ece-564-convolutional-neural-network-accelerator

A Verilog implementation of a CNN accelerator.

eigenvector

POSSUMM - PCA of Sparse, SUper Massive Matrices

es203-coa-cnn

ES-203 Computer Organization & Architecture CNN on FPGA board

external-attention-tensorflow

🍀 Tensorflow implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐

face_recognize

Matlab PCA 人脸识别

fft

Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm

fft_r2sdf

Radix 2 DIT FFT Single Path Delay Feedback

fpga-cnn

FPGA implementation of Cellular Neural Network (CNN)

fpga-ddr-sdram

An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。

fpga-jpeg-ls-encoder

An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。

fpga-sdcard-reader-spi

An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。

fpga-usb-device

An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

fpgaandgames

FPGA实现各种小游戏，学习并快乐着