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aes-opencl

AES-OpenCL - An AES implementation in OpenCL. This is the source code for my Bachelor's diploma. I did research on accelerating cryptographic algorithms using parallel computing languages (eg. OpenCL), in order make use of the full power of graphic processing units.

ava-core

A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)

avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

awesome-hdl

A curated list of awesome HDL, libraries, typical implementation and references.

awesome-open-hardware-verification

A List of Free and Open Source Hardware Verification Tools and Frameworks

basekit-code-samples

betrusted-soc

Betrusted main SoC design

boyi

A systematic framework for automatically deciding the right execution model for OpenCL applications on FPGAs

cae-lab

Lab Material for CAE

ccbench

Memory System Microbenchmarks

cdc_fifo_design

Multi-bit Synchronization across Clock Domains

chip-knn

[FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs

chisel3

Chisel 3: A Modern Hardware Design Language

cho

CHO is a benchmark suite for OpenCL FPGA Accelerators

clock-domain-crossing

In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.

cltune

CLTune: An automatic OpenCL & CUDA kernel tuner

comet

RISC-V ISA based 32-bit processor written in HLS

core-v-cores

CORE-V Family of RISC-V Cores

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cores-swerv

SweRV EH1 core

cores-swerv-eh2

crypto-algorithms

Basic implementations of standard cryptography algorithms, like AES and SHA-1.

cryptographic-algorithms

SHA-1, SHA-2, SHA-3, SM3, SM4, DES, AES implemented in C++

csi2rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

dac-17-ocl-fpga-profiling

Sample code for the DAC-17 paper

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

dseframe

esifhpc2

Benchmark collection used for NREL's ESIF-HPC-2 procurement and acceptance.