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api-config-chipsalliance

A Scala library for Context-Dependent Evironments

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

arithmetic

autoclonetype2_bug

automaton

barstools

Useful utilities for BAR projects

berkeley-hardfloat

block-inclusivecache-sifive

calculatephysicexercise

Homework

cde

A fork version from https://github.com/chipsalliance/api-config-chipsalliance with full git history, documentation and tests.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-circt

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

chisel-circt-binder

The Chisel Convert Phase implemented with JVM Panama

chisel-panama-standalone-plugin

chisel-testers

Provides various testers for chisel users

chisel3

Chisel 3

chiselminer-opensource

sha256d mining chip written by chisel.

chiselmodel

This is a experimental library interacting Chisel based design to foreign language with DPI, to inject arbitrary software model to Chisel and simulate together.

chiselv

A RISC-V Core (RV32I) written in Chisel HDL

circt

Circuit IR Compilers and Tools

clx

TL Serdes

copris

Fork from http://bach.istc.kobe-u.ac.jp/copris

cva6-wrapper

Wrapper for ETH Ariane Core

diplomacy

Standalone implementation to diplomacy.(WIP)

diplomatictester

VIP library for you TileLink IP

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

f2qr

felix-infra

The entry point of Felix Universe.

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firesim-hw