Comments (2)
No, the predicate memory instructions remain unimplemented in RTL, but they can be emulated with a compare operation and a vector byte load/store. Modifying your code sample:
vpset vp0
vlbu vv1, (va1)
vcmpeq vp1, vv1, vs0
vlw vv1, (va0)
@!vp1 vfirst vs1, vv1
...
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Your suggestion works. Issue closed.
Thanks!
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