Topic: systemverilog Goto Github

👇 Here are 823 public repositories matching this topic...

agalimberti / nocrouter
systemverilog,RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
User: agalimberti
network-on-chip noc router systemverilog

chipsalliance / surelog
systemverilog,SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Organization: chipsalliance
verilog parser python-api parser-ast vpi systemverilog preprocessor vpi-api vpi-standard antlr antlr4-grammar uvm linter elaboration

chipsalliance / sv-tests
systemverilog,Test suite designed to check compliance with the SystemVerilog standard.
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/sv-tests-results/
systemverilog symbiflow verilog hdl rtl compliance-testing

chipsalliance / uhdm
systemverilog,Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
Organization: chipsalliance
vpi-api vpi-interface systemverilog listener serialization ieee-standard

chipsalliance / verible
systemverilog,Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Organization: chipsalliance
Home Page: https://chipsalliance.github.io/verible/
systemverilog lexer yacc syntax-tree linter formatter parser systemverilog-parser style-linter hacktoberfest

clash-lang / clash-compiler
systemverilog,Haskell to VHDL/Verilog/SystemVerilog compiler
Organization: clash-lang
Home Page: https://clash-lang.org/
haskell hardware-description-language fpga vhdl verilog systemverilog asic

dalance / sv-parser
systemverilog,SystemVerilog parser library fully compliant with IEEE 1800-2017
User: dalance
rust rust-crate verilog systemverilog parser

dalance / svlint
systemverilog,SystemVerilog linter
User: dalance
rust verilog systemverilog lint linter

dalance / svls
systemverilog,SystemVerilog language server
User: dalance
rust verilog systemverilog language-server

gupta409 / processor-uvm-verification
systemverilog,System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
User: gupta409
uvm systemverilog systemverilog-simulation verilog-hdl verilog processor

hdl-util / hdmi
systemverilog,Send video/audio over HDMI on an FPGA
Organization: hdl-util
Home Page: https://purisa.me/blog/hdmi-released/
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx

ic-lab-duth / risc-v-vector
systemverilog,Vector processor for RISC-V vector ISA
Organization: ic-lab-duth
vector-processor riscv risc-v systemverilog

jamieiles / 80x86
systemverilog,80186 compatible SystemVerilog CPU core and FPGA reference design
User: jamieiles
Home Page: https://www.jamieiles.com/80186/
fpga systemverilog x86 softcore 80186

juniper / open-register-design-tool
systemverilog,Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Organization: juniper
systemrdl jspec eda asic fpga registers uvm systemverilog register-descriptions systemrdl-compiler

loykylewong / fpga-application-development-and-simulation
systemverilog,《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
User: loykylewong
fpga verilog systemverilog digital-signal-processing dsp modelsim axi4 uart spi i2c

mikepopoloski / slang
systemverilog,SystemVerilog compiler and language services
User: mikepopoloski
verilog compiler systemverilog slang parse language-service

mpsu / aps
systemverilog,Методические материалы по разработке процессора архитектуры RISC-V
Organization: mpsu
Home Page: https://mpsu.github.io/APS/
fpga riscv systemverilog

mshr-h / vscode-verilog-hdl-support
systemverilog,HDL support for VS Code
User: mshr-h
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado

nic30 / hdlconvertor
systemverilog,Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
User: nic30
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python

nic30 / hwt
systemverilog,VHDL/Verilog/SystemC code generator, simulator API written in python/c++
User: nic30
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen

olofk / edalize
systemverilog,An abstraction library for interfacing EDA tools
User: olofk
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog

openhwgroup / core-v-mcu
systemverilog,This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
Organization: openhwgroup
Home Page: https://docs.openhwgroup.org/projects/core-v-mcu
microcontroller openhwgroup riscv systemverilog

openhwgroup / core-v-verif
systemverilog,Functional verification project for the CORE-V family of RISC-V cores.
Organization: openhwgroup
Home Page: https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html
risc-v systemverilog uvm verification

pulp-platform / axi
systemverilog,AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Organization: pulp-platform
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip

pulp-platform / cheshire
systemverilog,A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
Organization: pulp-platform
fpga riscv rtl-design simulation systemverilog asic

pymtl / pymtl3
systemverilog,Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
Organization: pymtl
pymtl hardware-generation python hdl verilog systemverilog open-source-hardware multi-level-modeling cycle-level-modeling rtl

rggen / rggen
systemverilog,Code generation tool for control and status registers
Organization: rggen
amba apb asic axi csr eda fpga ral register-descriptions rtl soc systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl wiki-documents wishbone-bus

splinedrive / kianriscv
systemverilog,RISC-V Linux SoC, marchID: 0x2b
User: splinedrive
riscv verilog fpga cpu linux bare-metal linuxsoc mmu rv32ima sv32

suoto / hdl_checker
systemverilog,Repurposing existing HDL tools to help writing better code
User: suoto
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server

taichi-ishitani / tnoc
systemverilog,Network on Chip Implementation written in SytemVerilog
User: taichi-ishitani
noc network-on-chip systemverilog amba amba-axi axi axi4 uvm

taichi-ishitani / tvip-axi
systemverilog,AMBA AXI VIP
User: taichi-ishitani
systemverilog uvm amba amba-axi axi axi4 vip

terostechnology / vscode-teroshdl
systemverilog,VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Organization: terostechnology
Home Page: https://terostechnology.github.io/terosHDLdoc/
verilog vhdl systemverilog fpga

trivialmips / nontrivial-mips
systemverilog,NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Organization: trivialmips
systemverilog mips fpga-soc-linux fpga-soc cpu fpga xilinx

trivialmips / trivialmips
systemverilog,MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
Organization: trivialmips
systemverilog mips fpga xilinx cpu fpga-soc

tymonx / logic
systemverilog,CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
User: tymonx
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification

veripool / verilog-mode
systemverilog,Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
Organization: veripool
Home Page: http://veripool.org/verilog-mode
verilog emacs-lisp verilog-mode systemverilog

veryl-lang / veryl
systemverilog,Veryl: A Modern Hardware Description Language
Organization: veryl-lang
rtl rust systemverilog verilog

vivekmalneedi / veridian
systemverilog,A SystemVerilog Language Server
User: vivekmalneedi
lsp-server systemverilog verilog language-server

vproc / vicuna
systemverilog,RISC-V Zve32x Vector Coprocessor
Organization: vproc
risc-v vector-processor coprocessor systemverilog

wangxuan95 / fpga-can
systemverilog,An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-CAN
can can-bus fpga verilog systemverilog rtl controller control-area-network

wangxuan95 / fpga-fixedpoint
systemverilog,A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库，提供算术运算、与浮点数的互相转换，包含单周期和流水线两种实现。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-FixedPoint
verilog rtl systemverilog fixedpoint arithmetic pipeline

wangxuan95 / fpga-foc
systemverilog,FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-FOC
fpga verilog systemverilog foc field-oriented-control motor bldc pmsm svpwm

wangxuan95 / fpga-ftdi245fifo
systemverilog,FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-ftdi245fifo
usb ft232h ft600 ft601 fpga systemverilog ipcore verilog rtl

wangxuan95 / fpga-jpeg-ls-encoder
systemverilog,An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-JPEG-LS-encoder
fpga verilog systemverilog jpeg-ls jpegls jls rtl image-compression image-encoder

wangxuan95 / fpga-mpeg2-encoder
systemverilog,FPGA-based high performance MPEG2 encoder for video compression. 基于 FPGA 的高性能 MPEG2 视频编码器，可实现视频压缩。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-MPEG2-encoder
fpga ip-core mpeg-2 mpeg2 systemverilog verilog video video-compression video-compressor video-encode

wangxuan95 / fpga-nfc
systemverilog,Build an NFC (RFID) card reader using FPGA and simple circuit instead of RFID-specfic chip. 用FPGA+分立器件电路搭建一个NFC(RFID)读卡器，不需要专门的RFID芯片。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-NFC
rfid nfc fpga verilog systemverilog iso14443 iso14443a

wangxuan95 / fpga-sdcard-reader
systemverilog,An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-SDcard-Reader
fpga rtl sdcard sd-card file-system verilog systemverilog sdio

wangxuan95 / fpga-sdfake
systemverilog,Imitate SDcard using FPGAs. 使用FPGA模拟(伪装) SD卡。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/FPGA-SDfake
rtl sdcard verilog systemverilog fpga sdio

wangxuan95 / ustc-rvsoc
systemverilog,An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
User: wangxuan95
Home Page: https://gitee.com/wangxuan95/USTC-RVSoC
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu

zachjs / sv2v
systemverilog,SystemVerilog to Verilog conversion
User: zachjs
systemverilog verilog conversion yosys