lvcargnini Goto Github PK

agnoster-zsh-theme

A ZSH theme designed to disclose information contextually, with a powerline aesthetic

arachne-pnr

Place and route tool for FPGAs

ariane

Ariane is a 6-stage RISC-V CPU

atom

:atom: The hackable text editor

berkeley-hardfloat

berkeley-softfloat-3

SoftFloat release 3

blaster

chisel-bootcamp

Generator Bootcamp Material: Learn Chisel the Right Way

chisel-template

A template project for beginning new Chisel work

chisel-tutorial

chisel tutorial exercises and answers

chisel3

Chisel 3

chisel3-wiki

Mirror of Chisel3 Github wiki https://github.com/ucb-bar/chisel3/wiki

colloquy

crypto-example

A short, proof-of-concept RSA and AES encryption program with OpenSSL

cryptraider

Learnign to code for Unreal 5

dbt-rise-riscv

an instruction set simulator based on DBT-RISE implementing the RISC-V ISA

doc

Documentation for NVDLA.

dot

verilog dot product lib

dsptools

A Library of Chisel3 Tools for Digital Signal Processing

embench-iot

The main Embench repository

esp-llvm

UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM

firrtl

Flexible Intermediate Representation for RTL

firrtl-interpreter

A scala based simulator for circuits described by a LoFirrtl file

fpnew

[UNRELEASED] Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

fpu

synthesiseable ieee 754 floating point library in verilog

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

glassfish

The Open Source Java EE Reference Implementation

gmm

Gaussian Mixture Models

greenlib

GreenLib official mirror, please use git.greensocs.com for issues and contributions

grift

Galois RISC-V ISA Formal Tools