Topic: axi Goto Github
Some thing interesting about axi
Some thing interesting about axi
axi,This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
User: abdelazeem201
axi,Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).
User: aranellindi
axi,A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
User: aryan-programmer
axi, A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
User: aryan-programmer
axi,The Atfox exTensible Interface (ATI) is a on-chip communication bus protocol, which support for ATI System Bus Structure
User: atfox272
axi,Hardware and Software Co-design implementations
User: bselimoglu
axi,Xilinx AXI VIP example of use
User: esynr3z
Home Page: https://positive-slack.github.io/blog/2021-04-24-xilinx-axi-verification-ip
axi,FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
User: florin623
axi,Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
User: gednyengs
axi,Synchronous and Asynchronous FIFO with AXI interface
User: gururavi
Home Page: https://github.com/gururavi/rtl
axi,A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Organization: hdl-modules
Home Page: https://hdl-modules.com
axi,An open-source HDL register code generator fast enough to run in real time.
Organization: hdl-registers
Home Page: https://hdl-registers.com/
axi,Implementation of the Advanced Encryption Standard in Chisel
Organization: hplp
axi,Сервис по подбору доступного жилья.
User: igor-sergeevich-po
Home Page: https://igor-sergeevich-po.github.io/affordable-housing/
axi,SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
User: kuoyaoming93
axi,Basic JTAG / AXI demonstration on Xilinx's FPGA.
User: matthieumichon
axi,Userspace I/O library for Xilinx AXI S2MM DMA
Organization: microtca-tech-lab
axi,Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.
User: mrengineer
axi,XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
User: mwrnd
axi,Learning Resources for AXI made by self
User: narendiran1996
axi,Utility for creating and modifying VHDL bus slave modules
User: olagrottvik
axi,ASIC for executing vectorized gradient descent on linear regression problems.
User: pkill37
axi,Pothos FPGA computational offload and buffer integration support
Organization: pothosware
Home Page: https://github.com/pothosware/PothosFPGA/wiki
axi,AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Organization: pulp-platform
axi,AXI to Peripheral Interconnect
Organization: pulp-platform
axi,Simple single-port AXI memory interface
Organization: pulp-platform
axi,Common SystemVerilog RTL modules for RgGen
Organization: rggen
Home Page: https://github.com/rggen/rggen
axi,OPAE porting to Xilinx FPGA devices.
User: rspwfpgas
axi,:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
User: stnolting
Home Page: https://neorv32.org
axi,Control and status register code generator toolchain
Organization: systemrdl
Home Page: http://peakrdl.readthedocs.io
axi,Network on Chip Implementation written in SytemVerilog
User: taichi-ishitani
axi,AMBA AXI VIP
User: taichi-ishitani
axi,This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"
User: tanerguven
axi,IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
User: vedranmv
axi,Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
Organization: wissance
axi,VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
User: yourigh
axi,SD-Card controller, using either SPI, SDIO, or eMMC interfaces
User: zipcpu
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