stnolting's Projects
A retro-style digital clock based on 74xx discrete logic chips
π Add capacitive touch buttons to any FPGA!
π Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
π₯ Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
π¦ Prebuilt Icarus Verilog simulator package for x64 Linux.
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Formal verification (experiments) targeting the NEORV32 RISC-V processor.
πΎ FreeRTOS port for the NEORV32 RISC-V Processor.
βοΈPort of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
π NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
β»οΈ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.
π² A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Arduino Platform for Embedded RISC-V Chips
π JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
π¦ Prebuilt RISC-V GCC toolchains for x64 Linux.
Connect to your GHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> vhpi_jtag <-VHPI-> GHDL
π A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).