For the records:

I think all of the non-osflow (TCL) scripts are broken (referencing the NEORV32 "home folder"). I will do some tests using Quartus, Radiant and Vivado and update those scripts.

Hi, I am fairly new to FPGA and RISCV design. I have been trying to get the RV32E extension to work on the example UPduino project. A few months ago I was able to successfully setup the default provided project but unable to get RV32E to run with an example program. Recently I came back to it and redownloaded the example after the current rv32e prebuilt compiler was committed. Now I cannot get the default project to synthesize in Lattice Radiant. It gives an error saying 'neorv32_cpu_cp_cond is not compiled in library neorv32'. I've also tried using an open-source toolchain but I get an error saying 'no such command: ghdl' even though I have the latest version of ghdl installed on ubuntu. Any advice for the issue above and implementing RV32E with an example program would be much appreciated!

I assume the error comes from Github renaming the master branch to main ...
As I'm not very familiar with git submodules maybe some one can help here or fix this?

$ git clone --recurse-submodules --remote-submodules https://github.com/stnolting/neorv32-setups.git
Cloning into 'neorv32-setups'...
remote: Enumerating objects: 632, done.
remote: Counting objects: 100% (293/293), done.
remote: Compressing objects: 100% (188/188), done.
remote: Total 632 (delta 138), reused 197 (delta 102), pack-reused 339
Receiving objects: 100% (632/632), 332.16 KiB | 1.81 MiB/s, done.
Resolving deltas: 100% (305/305), done.
Submodule 'constraints' (https://github.com/hdl/constraints) registered for path 'constraints'
Submodule 'neorv32' (https://github.com/stnolting/neorv32) registered for path 'neorv32'
Cloning into '/home/torsten/Projects/github.com/neorv32-setups/constraints'...
remote: Enumerating objects: 1471, done.        
remote: Counting objects: 100% (112/112), done.        
remote: Compressing objects: 100% (45/45), done.        
remote: Total 1471 (delta 72), reused 84 (delta 63), pack-reused 1359        
Receiving objects: 100% (1471/1471), 3.11 MiB | 5.91 MiB/s, done.
Resolving deltas: 100% (699/699), done.
Cloning into '/home/torsten/Projects/github.com/neorv32-setups/neorv32'...
remote: Enumerating objects: 26299, done.        
remote: Counting objects: 100% (854/854), done.        
remote: Compressing objects: 100% (397/397), done.        
remote: Total 26299 (delta 565), reused 714 (delta 456), pack-reused 25445        
Receiving objects: 100% (26299/26299), 186.23 MiB | 3.45 MiB/s, done.
Resolving deltas: 100% (18045/18045), done.
fatal: Needed a single revision
Unable to find current origin/master revision in submodule path 'constraints'

Hi @stnolting

According to what we discussed the other day:

It occurs to me that maybe the arty option can be added to the CI list of implementations.
That would be awesome! Feel free to propose a PR for that 😉

I've made the following container:

• ghcr.io/unike267/containers/impl-arty:latest

With:

• GHDL + yosys + GHDL yosys plugin + nextpnr-xilinx + prjxray

To perform synthesis + implementation + generate bitstream on the boards:

• Arty A7 35t
• Arty A7 100t

I've built and pushed this container through continuous integration in the repository:

• gh: Unike267/Containers

I've tested the synthesis + implementation + generate bitstream of the NEORV32 in the branch:

• Unike267/Containers/tree/neorv32-setups

And as we can see in these jobs the bitstreams are generated correctly.

I've tested them on Arty A7 35t & 100t and they work fine.

Now the challenge is to add these implementations through the CI of the neorv32-setups repository.

But before starting this work we should wonder, is this implementation really useful? 🤔

I mean, the implementation is limited because dsp can't be used. The yosys options -nodsp and -nolutram are necessary to perform the implementation.

However, if you are really interested in implementing this option, I could try to solve the challenge of adding arty support through continuous integration of the neorv32-setups.

In my opinion it would be interesting to support Xilinx implementation through FOSS tools.

What do you think?

/cc @umarcor

I compiled the default image using Lattice Radiant 2023 and flashed it to the UPduino 3.1. However, after powering the board, I don't see the LED blink at 2 Hz and don't see any output on the UART interface. From the constraints, it looks like UART Tx is pin 38 on the board and UART Rx is pin 28. Can you help me debug this issue?

I don't really understand the error messages. It complains about:
ERROR - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd(169): formal io_gpio_en is not declared. VHDL-1084
which simply isn't true, and from then on it complains about top module not being in the design, I guess most errors come from the first one, but I don't understand why.

`Starting: "prj_run Export -impl impl_1"

synthesis: version Radiant Software (64-bit) 2022.1.0.52.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved.
Tue Feb 21 14:55:17 2023

Command Line: C:\lscc\radiant\2022.1\ispfpga\bin\nt64\synthesis.exe -f neorv32_upduino_v3_impl_1_lattice.synproj -gui -msgset C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/promote.xml

INFO - synthesis: Lattice Synthesis Engine Launched.
Synthesis options:
The -a option is iCE40UP.
The -t option is SG48.
The -sp option is High-Performance_1.2V.
The -p option is iCE40UP5K.

##########################################################

Lattice Family : iCE40UP

Device : iCE40UP5K

Package : SG48

Performance Grade : High-Performance_1.2V

INFO - User-Selected Strategy Settings
Optimization goal = Area
Top-level module name = neorv32_upduino_v3_top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
RWCheckOnRam = 0

BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = auto (Default)
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
Output HDL file name = neorv32_upduino_v3_impl_1.vm.
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-sdc option: SDC file input is neorv32_upduino_v3_impl_1_cpe.ldc.
ERROR - LDC file neorv32_upduino_v3_impl_1_cpe.ldc does not exist.
child process exited abnormally
Fail to run synthesis -f neorv32_upduino_v3_impl_1_lattice.synproj -gui -msgset C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/promote.xml
Done: error code 1

** Lattice Synthesis Engine **

"C:/lscc/radiant/2022.1/tcltk/windows/bin/tclsh" "neorv32_upduino_v3_impl_1_synthesize.tcl"

cpe -f neorv32_upduino_v3_impl_1.cprj system_pll.cprj -a iCE40UP -o neorv32_upduino_v3_impl_1_cpe.ldc
WARNING - No user LDC/SDC file specified in the project.
Top module name (Verilog): system_pll
INFO - C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v(11): compiling module system_pll. VERI-1018
INFO - C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/system_pll/rtl/system_pll.v(107): compiling module system_pll_ipgen_lscc_pll(DIVR="0",DIVF="0",DIVQ="3",FEEDBACK_PATH="PHASE_AND_DELAY",FILTER_RANGE="2",FREQUENCY_PIN_REFERENCECLK="24.000000"). VERI-1018
INFO - C:/lscc/radiant/2022.1/ispfpga/../cae_library/synthesis/verilog/iCE40UP.v(428): compiling module PLL_B(FEEDBACK_PATH="PHASE_AND_DELAY",DIVQ="3",FILTER_RANGE="2",FREQUENCY_PIN_REFERENCECLK="24.000000"). VERI-1018
Last elaborated design is system_pll()
Source compile complete.
INFO - Setting neorv32_upduino_v3_top as top module.
WARNING - No user LDC/SDC file specified in the project.
Analyzing Verilog file c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v. VERI-1482
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(1): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_addsub.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_addsub.v(40): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/adder_subtractor/rtl/lscc_add_sub.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(2): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_add.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_add.v(50): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/adder/rtl/lscc_adder.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(3): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_complex_mult.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_complex_mult.v(52): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/complex_mult/rtl/lscc_complex_mult.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(4): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_counter.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_counter.v(39): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/counter/rtl/lscc_cntr.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(5): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_fifo.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_fifo.v(44): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/fifo/rtl/lscc_fifo.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(6): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_fifo_dc.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_fifo_dc.v(47): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/fifo_dc/rtl/lscc_fifo_dc.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(7): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_mac.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_mac.v(52): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/mult_accumulate/rtl/lscc_mult_accumulate.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(8): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_multaddsubsum.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_multaddsubsum.v(53): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/mult_add_sub_sum/rtl/lscc_mult_add_sub_sum.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(9): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_multaddsub.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_multaddsub.v(52): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/mult_add_sub/rtl/lscc_mult_add_sub.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(10): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_mult.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_mult.v(51): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/multiplier/rtl/lscc_multiplier.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(11): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dp.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dp.v(48): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(12): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dq.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dq.v(45): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(13): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_rom.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_rom.v(45): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/rom/rtl/lscc_rom.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(14): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_sub.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_sub.v(50): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../common/subtractor/rtl/lscc_subtractor.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(15): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dp_be.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dp_be.v(49): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/ram_dp/rtl/lscc_ram_dp.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(16): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dq_be.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ram_dq_be.v(45): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/../avant/ram_dq/rtl/lscc_ram_dq.v. VERI-1328
INFO - c:/lscc/radiant/2022.1/ip/pmi/pmi_ice40up.v(17): analyzing included file c:/lscc/radiant/2022.1/ip/pmi/pmi_dsp.v. VERI-1328
Analyzing Verilog file system_pll.v. VERI-1482
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd(39): analyzing package neorv32_package. VHDL-1014
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd(2260): analyzing package body neorv32_package. VHDL-1013
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd(2580): analyzing package neorv32_bootloader_image. VHDL-1014
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_package.vhd(2597): analyzing package neorv32_application_image. VHDL-1014
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_application_image.vhd(8): analyzing package body neorv32_application_image. VHDL-1013
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_boot_rom.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_boot_rom.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_boot_rom.vhd(43): analyzing entity neorv32_boot_rom. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_boot_rom.vhd(58): analyzing architecture neorv32_boot_rom_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bootloader_image.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bootloader_image.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bootloader_image.vhd(8): analyzing package body neorv32_bootloader_image. VHDL-1013
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_busswitch.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_busswitch.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_busswitch.vhd(45): analyzing entity neorv32_busswitch. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_busswitch.vhd(91): analyzing architecture neorv32_busswitch_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bus_keeper.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bus_keeper.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bus_keeper.vhd(46): analyzing entity neorv32_bus_keeper. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_bus_keeper.vhd(70): analyzing architecture neorv32_bus_keeper_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cfs.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cfs.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cfs.vhd(49): analyzing entity neorv32_cfs. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cfs.vhd(78): analyzing architecture neorv32_cfs_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu.vhd(42): analyzing entity neorv32_cpu. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu.vhd(111): analyzing architecture neorv32_cpu_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_alu.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_alu.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_alu.vhd(44): analyzing entity neorv32_cpu_alu. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_alu.vhd(80): analyzing architecture neorv32_cpu_cpu_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_bus.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_bus.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_bus.vhd(44): analyzing entity neorv32_cpu_bus. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_bus.vhd(85): analyzing architecture neorv32_cpu_bus_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_control.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_control.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_control.vhd(52): analyzing entity neorv32_cpu_control. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_control.vhd(133): analyzing architecture neorv32_cpu_control_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(58): analyzing entity neorv32_cpu_cp_fpu. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(80): analyzing architecture neorv32_cpu_cp_fpu_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(1178): analyzing entity neorv32_cpu_cp_fpu_normalizer. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(1200): analyzing architecture neorv32_cpu_cp_fpu_normalizer_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(1565): analyzing entity neorv32_cpu_cp_fpu_f2i. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd(1585): analyzing architecture neorv32_cpu_cp_fpu_f2i_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd(51): analyzing entity neorv32_cpu_cp_bitmanip. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd(73): analyzing architecture neorv32_cpu_cp_bitmanip_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd(46): analyzing entity neorv32_cpu_cp_muldiv. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd(67): analyzing architecture neorv32_cpu_cp_muldiv_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd(45): analyzing entity neorv32_cpu_cp_shifter. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd(65): analyzing architecture neorv32_cpu_cp_shifter_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_decompressor.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_decompressor.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_decompressor.vhd(42): analyzing entity neorv32_cpu_decompressor. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_decompressor.vhd(55): analyzing architecture neorv32_cpu_decompressor_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_regfile.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_regfile.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_regfile.vhd(54): analyzing entity neorv32_cpu_regfile. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_cpu_regfile.vhd(78): analyzing architecture neorv32_cpu_regfile_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dm.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dm.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dm.vhd(58): analyzing entity neorv32_debug_dm. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dm.vhd(88): analyzing architecture neorv32_debug_dm_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dtm.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dtm.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dtm.vhd(41): analyzing entity neorv32_debug_dtm. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_debug_dtm.vhd(70): analyzing architecture neorv32_debug_dtm_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_fifo.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_fifo.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_fifo.vhd(42): analyzing entity neorv32_fifo. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_fifo.vhd(67): analyzing architecture neorv32_fifo_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gpio.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gpio.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gpio.vhd(42): analyzing entity neorv32_gpio. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gpio.vhd(62): analyzing architecture neorv32_gpio_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gptmr.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gptmr.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gptmr.vhd(47): analyzing entity neorv32_gptmr. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_gptmr.vhd(66): analyzing architecture neorv32_gptmr_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd(45): analyzing entity neorv32_icache. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd(73): analyzing architecture neorv32_icache_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd(385): analyzing entity neorv32_icache_memory. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_icache.vhd(414): analyzing architecture neorv32_icache_memory_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_mtime.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_mtime.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_mtime.vhd(45): analyzing entity neorv32_mtime. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_mtime.vhd(61): analyzing architecture neorv32_mtime_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_neoled.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_neoled.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_neoled.vhd(56): analyzing entity neorv32_neoled. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_neoled.vhd(80): analyzing architecture neorv32_neoled_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_pwm.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_pwm.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_pwm.vhd(45): analyzing entity neorv32_pwm. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_pwm.vhd(67): analyzing architecture neorv32_pwm_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_spi.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_spi.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_spi.vhd(46): analyzing entity neorv32_spi. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_spi.vhd(73): analyzing architecture neorv32_spi_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_sysinfo.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_sysinfo.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_sysinfo.vhd(45): analyzing entity neorv32_sysinfo. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_sysinfo.vhd(99): analyzing architecture neorv32_sysinfo_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_top.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_top.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_top.vhd(47): analyzing entity neorv32_top. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_top.vhd(239): analyzing architecture neorv32_top_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(46): analyzing entity neorv32_trng. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(63): analyzing architecture neorv32_trng_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(292): analyzing entity neotrng. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(310): analyzing architecture neotrng_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(622): analyzing entity neotrng_cell. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_trng.vhd(638): analyzing architecture neotrng_cell_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_twi.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_twi.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_twi.vhd(47): analyzing entity neorv32_twi. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_twi.vhd(71): analyzing architecture neorv32_twi_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_uart.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_uart.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_uart.vhd(68): analyzing entity neorv32_uart. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_uart.vhd(99): analyzing architecture neorv32_uart_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wdt.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wdt.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wdt.vhd(50): analyzing entity neorv32_wdt. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wdt.vhd(74): analyzing architecture neorv32_wdt_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wishbone.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wishbone.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wishbone.vhd(55): analyzing entity neorv32_wishbone. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_wishbone.vhd(104): analyzing architecture neorv32_wishbone_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xirq.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xirq.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xirq.vhd(49): analyzing entity neorv32_xirq. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xirq.vhd(72): analyzing architecture neorv32_xirq_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_dmem.entity.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_dmem.entity.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_dmem.entity.vhd(39): analyzing entity neorv32_dmem. VHDL-1012
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_imem.entity.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_imem.entity.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_imem.entity.vhd(42): analyzing entity neorv32_imem. VHDL-1012
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_dmem.ice40up_spram.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_dmem.ice40up_spram.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_dmem.ice40up_spram.vhd(48): analyzing architecture neorv32_dmem_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_imem.ice40up_spram.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_imem.ice40up_spram.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_imem.ice40up_spram.vhd(48): analyzing architecture neorv32_imem_rtl. VHDL-1010
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd(48): analyzing entity neorv32_upduino_v3_top. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd(74): analyzing architecture neorv32_upduino_v3_top_rtl. VHDL-1010
ERROR - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd(169): formal io_gpio_en is not declared. VHDL-1084
ERROR - Stopping Synthesis Tool flow due to error.
ERROR - c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd(244): unit neorv32_upduino_v3_top_rtl ignored due to previous errors. VHDL-1284
ERROR - Stopping Synthesis Tool flow due to error.
VHDL file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd ignored due to errors. VHDL-1482
ERROR - Failed to analyze the file c:/users/sslayer/desktop/neorv32-setups/radiant/upduino_v3/neorv32_upduino_v3_top.vhd.
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd. VHDL-1481
Analyzing VHDL file c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd

INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd(48): analyzing entity neorv32_xip. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd(82): analyzing architecture neorv32_xip_rtl. VHDL-1010
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd(476): analyzing entity neorv32_xip_phy. VHDL-1012
INFO - c:/users/sslayer/desktop/neorv32-setups/neorv32/rtl/core/neorv32_xip.vhd(501): analyzing architecture neorv32_xip_phy_rtl. VHDL-1010
INFO - The default VHDL library search path is now "C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/impl_1". VHDL-1504
ERROR - Top module neorv32_upduino_v3_top does not exist in the design.
ERROR - Unknown top module language type.
Top module name (Verilog, mixed language): neorv32_upduino_v3_top
module neorv32_upduino_v3_top in library work is not yet analyzed. VERI-1486
ERROR - Failed to elaborate the design neorv32_upduino_v3_top.
WARNING - Source compilation failed.
WARNING - Error processing input files.
ERROR - Processing input files had at least one error. Exiting.

synthesis -f neorv32_upduino_v3_impl_1_lattice.synproj
synthesis: version Radiant Software (64-bit) 2022.1.0.52.3

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2022 Lattice Semiconductor Corporation, All rights reserved.
Tue Feb 21 14:55:24 2023

Command Line: C:\lscc\radiant\2022.1\ispfpga\bin\nt64\synthesis.exe -f neorv32_upduino_v3_impl_1_lattice.synproj -gui -msgset C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/promote.xml

INFO - synthesis: Lattice Synthesis Engine Launched.
Synthesis options:
The -a option is iCE40UP.
The -t option is SG48.
The -sp option is High-Performance_1.2V.
The -p option is iCE40UP5K.

##########################################################

Lattice Family : iCE40UP

Device : iCE40UP5K

Package : SG48

Performance Grade : High-Performance_1.2V

INFO - User-Selected Strategy Settings
Optimization goal = Area
Top-level module name = neorv32_upduino_v3_top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
RWCheckOnRam = 0

BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = auto (Default)
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
Output HDL file name = neorv32_upduino_v3_impl_1.vm.
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-sdc option: SDC file input is neorv32_upduino_v3_impl_1_cpe.ldc.
ERROR - LDC file neorv32_upduino_v3_impl_1_cpe.ldc does not exist.
child process exited abnormally
Fail to run synthesis -f neorv32_upduino_v3_impl_1_lattice.synproj -gui -msgset C:/Users/sslayer/Desktop/neorv32-setups/radiant/UPduino_v3/promote.xml
Done: error code 1`

First a great thank you for the great stuff you provide. I just recently started to work with RV and do digital logic since 1996.

While bringing a mini implementation up with all internal memories in both Vivado and Quartus as well as Lattice I noticed that mainly the optimizers like to optimize away ROM - content leading to futher "optisation" of the RAM rendering synthesis faulty.

I changed the following for quartus (Board: DE0-NANO):
=>Use dedicated ROM/RAM components to infer RAMS, split up processes
=>Blink Check and Debugging okay
For Modelsim:
=>Guard read access (I use 3 kbyte ROM/RAM) from illeagal addresses
=>Blink Check and Debugging okay
For Vivado (Board: Colorlight i9+):
=>Use dont_touch and keep attributes on the write-enables,read-enables of the RAM and address, data on ROM/ROM
=>Blink Check and Debugging okay
For Lattice (Board: Colorlight i9):
=>So far no success, RAM access (dmem) not working
but I will try to get it running as well, need to prevent the Synplify Optimizer from overdoing.

For GoWin (Arora Board):
=> Project just started.

If you have any hints on that pls let me know. I can also contribute generic RAMs and a changed ROM.

Hi,

I am exploring iCEBreaker board to run various RISC-V CPUs. I am trying to run the UP5KDemo version of the processor. I am able to synthesize the processor and program the flash . I am able to send application files via Terminal programs and the application runs fine. However, if i try to save the executable to flash of boot from flash, I get ERR_FLSH error and the processor stops working. Am i missing something while synthesizing the code?
I checked the jumpers on iCEBreaker board, they are in their default position. So It should be possible for iCEBreaker to access the flash.
Looking forward to your support.

Since we switched to entity instantiation (in #103) we have some problems with the open-source synthesis flow:

1 - The "Minimal" configuration fails to build

Currently, we only have one setup that uses the "Minimal" processor template: the FOMU setup. The flow fails during yosys's VHDL import:

Linux:

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 4.0.0-dev (v3.0.0-329-g63eee3d6b) [Dunoon edition]
Compiled with unknown compiler version
Target: x86_64-linux-gnu
/github/workspace/osflow/
Command line:

Exception CONSTRAINT_ERROR raised
Exception information:
raised CONSTRAINT_ERROR : elab-vhdl_context.adb:453 discriminant check failed
******************************************************************
ERROR: vhdl import failed.

(-> https://github.com/stnolting/neorv32-setups/actions/runs/5619677963/job/15227203878#step:4:90)

MIGNW:

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 4.0.0-dev (3.0.0.r147.g6c56631a7) [Dunoon edition]
Compiled with unknown compiler version
Target: x86_64-w64-mingw32
D:\a\neorv32-setups\neorv32-setups\osflow\
Command line:
D:\a\_temp\msys64\mingw64\bin\yosys.exe -D PVT=1 -p ghdl --std=08 --workdir=build -Pbuild --no-formal neorv32_Fomu_BoardTop_Minimal;    synth_ice40   -top neorv32_Fomu_BoardTop_Minimal -dsp   -json neorv32_Fomu_pvt_Minimal.json
Exception CONSTRAINT_ERROR raised
Exception information:
raised CONSTRAINT_ERROR : elab-vhdl_context.adb:453 discriminant check failed
******************************************************************
ERROR: vhdl import failed.

(-> https://github.com/stnolting/neorv32-setups/actions/runs/5619901737/job/15227826811#step:5:147)

First I thought this might be a problem with the core's file list / compile order. But even with the changes from #107 this problem remains. So I am not sure if this is really caused by something related to the entity instantiation change. Maybe we have an actual RTL issue here, since the "Minimal" setup appears the only one that disables the processor-internal bootloader (INT_BOOTLOADER_EN => false,)... 🤔

2 - Problems with MINGW64's ECP5 support

The OrangeCrab and ULX3S setups fail. Both boards are based on Lattice ECP5 FPGAs. It seems like there is a problem with MING's nextpnr-ecp5 as the plain-Linux flows for these boards run without problems.

nextpnr-ecp5 \
  --25k --package CSFBGA285 --ignore-loops --timing-allow-fail \
  --lpf constraints/OrangeCrab.lpf \
  --json neorv32_OrangeCrab_r02-25F_MinimalBoot.json \
  --textcfg neorv32_OrangeCrab_r02-25F_MinimalBoot.cfg 2>&1 | tee nextpnr-report.txt
/bin/sh: line 2: nextpnr-ecp5: command not found

(-> https://github.com/stnolting/neorv32-setups/actions/runs/5619677963/job/15227202982#step:5:3413)

3 - ICESugar's "Minimal" configuration is incorrect

The neorv32_iCESugar-v1.5_BoardTop_Minimal.vhd setup should use the "Minimal" processor template configuration but uses the "MinimalBoot" one instead. This is just a minor issue and can be fixed easily.

However, I assume that the fixed configuration would fail because of (1).

Hi @stnolting

Since this commit the implementation in Vivado crashes. It is freezes in the line:

# launch_runs impl_1 -to_step write_bitstream -jobs 4

That is, some change between commit 5486aa4 and commit 46baf5a causes a failure in the implementation with vivado.

As we can see locally in the following image:

It should be noted that also crashes in my gitlab continuous integration.

The vivado version is v2022.2.

Note that until commit 5486aa4 there was no problem with the implementation so I am going to debug from 5486aa4, commit by commit to see what is causing the failure and I will update the progress on this issue.

I hope that we will solve it quickly! 😃

Cheers!

/cc @umarcor

yosys \
-p \
"ghdl --std=08 --workdir=build -Pbuild --no-formal neorv32_iCESugarv15_BoardTop_MinimalBoot; \
synth_ice40 \
-top neorv32_iCESugarv15_BoardTop_MinimalBoot -dsp \
-json neorv32_iCESugar-v1.5_MinimalBoot.json" 2>&1 | tee yosys-report.txt
ERROR: No such command: ghdl (type 'help' for a command overview)
nextpnr-ice40 \
--up5k --package sg48 --ignore-loops --timing-allow-fail \
--pcf ../constraints/board/iCESugar-v1.5/constraints.pcf \
--json neorv32_iCESugar-v1.5_MinimalBoot.json \
--asc neorv32_iCESugar-v1.5_MinimalBoot.asc 2>&1 | tee nextpnr-report.txt
ERROR: Failed to open JSON file 'neorv32_iCESugar-v1.5_MinimalBoot.json'.

The TWI pins for the UPduino top level are marked as inout:

    twi_sda_io  : inout std_logic;
    twi_scl_io  : inout std_logic;

But, the CPU top-level has separate input and output pins for the SDA and SCL lines:

    twi_sda_i      : in  std_ulogic := 'H'; -- serial data line sense input
    twi_sda_o      : out std_ulogic; -- serial data line output (pull low only)
    twi_scl_i      : in  std_ulogic := 'H'; -- serial clock line sense input
    twi_scl_o      : out std_ulogic; -- serial clock line output (pull low only)

How would you advise reconciling this difference?

Hello,

First, thank you for putting in the continued effort into this project. I just got involved in RISCV and this looks to be great project to get my feet wet. I'm working on a UPduino board using Lattice Semiconductor's Radiant toolchain. When I try to synthesize the project, I get the following errors:

Error	2049990	Project	ERROR <2049990> - D:/Documents/lattice/neorv32-setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd(88,25-88,31) (VHDL-1241) 'rden_i' is not declared [neorv32_dmem.ice40up_spram.vhd:88]	
Error	2049990	Project	ERROR <2049990> - D:/Documents/lattice/neorv32-setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd(87,23-87,55) (VHDL-1241) 'addr_i' is not declared [neorv32_dmem.ice40up_spram.vhd:87]	
Error	2049990	Project	ERROR <2049990> - D:/Documents/lattice/neorv32-setups/radiant/UPduino_v3/neorv32_dmem.ice40up_spram.vhd(88,35-88,41) (VHDL-1241) 'wren_i' is not declared [neorv32_dmem.ice40up_spram.vhd:88]	

Reviewing the neorv32_demem.ice40up_spram.vhd VHDL file, I don't see the definition of rden_i, addr_i, and wren_i:

  signal acc_en : std_ulogic;
  signal mem_cs : std_ulogic;
  signal rdata  : std_ulogic_vector(31 downto 0);
  signal rden   : std_ulogic;

  -- SPRAM signals --
  signal spram_clk   : std_logic;
  signal spram_addr  : std_logic_vector(13 downto 0);
  signal spram_di_lo : std_logic_vector(15 downto 0);
  signal spram_di_hi : std_logic_vector(15 downto 0);
  signal spram_do_lo : std_logic_vector(15 downto 0);
  signal spram_do_hi : std_logic_vector(15 downto 0);
  signal spram_be_lo : std_logic_vector(03 downto 0);
  signal spram_be_hi : std_logic_vector(03 downto 0);
  signal spram_we    : std_logic;
  signal spram_pwr_n : std_logic;

  acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = DMEM_BASE(hi_abb_c downto lo_abb_c)) else '0';
  mem_cs <= acc_en and (rden_i or wren_i);

Am I missing something?

Thanks

Hi,

I have a hardware mentioned in the topic.
I have working "hello world" UART upload example.
Can I prepare such example setup for this ?

# ecppack
Mingw-w64 runtime failure:
32 bit pseudo relocation at 00007FF784896911 out of range, targeting 00007FFAB975DA10, yielding the value 0000000334EC70FB.

That is producing failures in some CI jobs. GHDL, Yosys and nextpnr are successful, bit the bitstream generation crashes when running ecppack.