DMEM/IMEM Portability of Closed Toolchains / Vivado / Intel / Lattice / GoWin about neorv32-setups HOT 4 OPEN

Thank you for your reply, I am now working on the full system first on the Altera/Intel toolchain and will come back to this once I am finished as debugging on Quartus is the most efficient for me.

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Thank you for your reminder... We are working on a multitude of aspects, please allow another week and I will follow up on this and other items.

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Hey @timaosan!

First of all, the memory modules from neorv32/rtl/core/mem were designed in a platform-agnostic way. So they can (should) be synthesized for any platform resulting in the correct inference of block RAM. I have tested this on Xilinx (Vivado), Intel (Quartus) and Lattice (Diamond + Radiant) FPGAs.

I use 3 kbyte ROM/RAM

Better use a power of two for the memory sizes - otherwise the synthesizer might have issues inferring block RAM.

For Lattice (Board: Colorlight i9):
=>So far no success, RAM access (dmem) not working

Have you checked the final synthesis reports? There should be a notification if the tool was not able to infer block RAM.

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Are there any updates on this?
Otherwise we can close this (for now 😉).

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