Topic: vlsi Goto Github
Some thing interesting about vlsi
Some thing interesting about vlsi
vlsi,Verilog Implementation of 32-bit Floating Point Adder
User: ahirsharan
vlsi,EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
User: ahmed-agiza
Home Page: https://edaviewer.com
vlsi,30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
User: akashtailor-exe
vlsi,Branch Predictor Optimization for BlackParrot
User: andreaskuster
Home Page: https://github.com/andreaskuster/black-parrot
vlsi,Some simple examples for the Magic VLSI physical chip layout tool.
User: andrsmllr
vlsi,Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
User: angelojacobo
vlsi,Create fast and efficient standard cell based adders, multipliers and multiply-adders.
User: antonblanchard
vlsi,Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
Organization: arm-university
vlsi,Gate-level visualization generator for SKY130-based chip designs.
User: asinghani
vlsi,ACT hardware description language and core tools.
Organization: asyncvlsi
Home Page: http://avlsi.csl.yale.edu/act
vlsi,Top-level repository for the ACT EDA flow
Organization: asyncvlsi
Home Page: https://avlsi.csl.yale.edu/act/
vlsi,AMC: Asynchronous Memory Compiler
Organization: asyncvlsi
Home Page: http://avlsi.csl.yale.edu/act/doku.php?id=amc:start
vlsi,Standard Cell Library based Memory Compiler using FF/Latch cells
Organization: aucohl
vlsi,Delta Sigma DAC FPGA
User: briansune
Home Page: https://briansune.github.io/Delta-Sigma-DAC-Verilog/
vlsi,Doug is a WIP semi-automated to full manual VLSI Analog and Mixed Signal CAD design tool built with Bevy and Layout21
User: colepoirier
vlsi,A browser-based SPICE circuit simulator
User: danchitnis
Home Page: https://EEsim.dev
vlsi,A modern and open-source cross-platform software for chips reverse engineering.
Organization: degatecommunity
Home Page: https://www.degate.org
vlsi,Simple pin assignment generator for IC case
User: idoka
Home Page: http://idoka.ru/php-asic-pinout-generator/
vlsi,DATC RDF
Organization: ieee-ceda-datc
vlsi,Electrical And Electronic Engineering Course Materials
User: imsanjoykb
Home Page: https://imsanjoykb.github.io/
vlsi,A LEF/DEF Utility.
User: jinwookjungs
vlsi,demo on simple channel router
User: levibyte
vlsi,genetic algorithm usage for routing optimization ( pyqt )
User: levibyte
vlsi,Deep learning toolkit-enabled VLSI placement
User: limbo018
vlsi,VLSI EDA Global Router
User: luckyrantanplan
Home Page: http://www.cs.nthu.edu.tw/~tcwang/nthuroute/
vlsi,Deep Learning & VLSI Crash Course for New Members
Organization: mediaic
vlsi,CAD framework tool on top of Qt
Organization: mm-project
vlsi,Open source software for chip reverse engineering.
User: nitram2342
Home Page: http://www.degate.org/
vlsi,A High-performance Timing Analysis Tool for VLSI Systems
Organization: opentimer
vlsi,A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Organization: opentimer
vlsi,phoeniX RISC-V Processor
Organization: phoenix-digital-design
vlsi,GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Organization: purdue-onchip
vlsi,Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
User: srohit0
Home Page: http://amzn.to/2paZ53b
vlsi,All the projects and assignments done as part of VLSI course.
User: subzer0811
vlsi,System Verilog BootCamp
User: suntrakanesh
vlsi,Gatery, a library for circuit design.
Organization: synogate
Home Page: https://www.synogate.com/gatery.html
vlsi,Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
User: tharunchitipolu
vlsi,OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Organization: the-openroad-project
Home Page: https://openlane.readthedocs.io/
vlsi,Online viewer of Xschem schematic files
Organization: tinytapeout
Home Page: https://xschem-viewer.com/
vlsi,Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
User: twweeb
vlsi,cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
User: ucdrstdenis
Home Page: https://ucdrstdenis.github.io/cdsAsync
vlsi,Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
User: varunnagpaal
vlsi,IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Organization: vlsi-eda
Home Page: https://tu-dresden.de/ing/informatik/ti/vlsi
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