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openlane2's Introduction

OpenLane

License: Apache 2.0 Python 3.8 or higher Code Style: black Checked with mypy Built with Nix

Open in Colab Documentation Build Status Badge Invite to the Open Source Silicon Slack

OpenLane is an ASIC infrastructure library based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for design exploration and optimization.

A reference flow, "Classic", performs all ASIC implementation steps from RTL all the way down to GDSII.

You can find the documentation here to get started. You can discuss OpenLane 2 in the #openlane-2 channel of the Efabless Open Source Silicon Slack.

OpenLane 2 is generally available for educators and for those implementing complex chips requiring custom implementation steps for which OpenLane 1 is not sufficiently flexible.

If you're looking to implement a project for the OpenMPW or chipIgnite shuttles, we recommend OpenLane 1 at this time.

from openlane.flows import Flow

Classic = Flow.factory.get("Classic")

flow = Classic(
    {
        "PDK": "sky130A",
        "DESIGN_NAME": "spm",
        "VERILOG_FILES": ["./src/spm.v"],
        "CLOCK_PORT": "clk",
        "CLOCK_PERIOD": 10,
    },
    design_dir=".",
)

flow.start()

Try it out

You can try OpenLane right in your browser, free-of-charge, using Google Colaboratory by following this link.

Installation

You'll need the following:

  • Python 3.8 or higher with PIP, Venv and Tkinter

Nix (Recommended)

Works for macOS and Linux (x86-64 and aarch64). Recommended, as it is more integrated with your filesystem and overall has less upload and download deltas.

See Nix-based installation in the docs for more info.

Docker

Works for Windows, macOS and Linux (x86-64 and aarch64).

See Docker-based installation in the docs for more info.

Do note you'll need to add --dockerized right after openlane in most CLI invocations.

Python-only Installation (Advanced)

You'll need to bring your own compiled utilities, but otherwise, simply install OpenLane as follows:

python3 -m pip install --upgrade openlane

Usage

In the root folder of the repository, you may invoke:

python3 -m openlane --pdk-root <path/to/pdk> </path/to/config.json>

To start with, you can try:

python3 -m openlane --pdk-root $HOME/.volare ./designs/spm/config.json

Publication

If you use OpenLane in your research, please cite the following paper.

  • M. Shalan and T. Edwards, “Building OpenLANE: A 130nm OpenROAD-based Tapeout-Proven Flow: Invited Paper,” 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-6. Paper
@INPROCEEDINGS{9256623,
  author={Shalan, Mohamed and Edwards, Tim},
  booktitle={2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, 
  title={Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper}, 
  year={2020},
  volume={},
  number={},
  pages={1-6},
  doi={}}

License

The Apache License, version 2.0.

Docker images distributed by Efabless Corporation under the same license.

Binaries bundled with OpenLane either via Cachix or Docker are distributed by Efabless Corporation and may fall under stricter open source licenses.

openlane2's People

Contributors

7fm avatar aidanmedcalf avatar calvbore avatar donn avatar hpretl avatar kareefardi avatar mo-hosni avatar mole99 avatar passant5 avatar prokie avatar smunaut avatar urish avatar

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openlane2's Issues

Yosys config params

ERROR: Module \sky130_fd_sc_hd__dlclkp_1 referenced in module \BYTE' in cell \genblk1.CG is not part of the design while having "SYNTH_ELABORATE_ONLY": "1" and "SYNTH_READ_BLACKBOX_LIB": "1".

tcl_reproducible.zip

PDN_MACRO_CONNECTIONS doesn't work. Value gets mangled.

The value that gets to the actual TCL script is mangled and not the actual string specified ...
This is what I put in my dict :

              "PDN_MACRO_CONNECTIONS": [
                       "top_I.*tt_um_I vccd1 vssd1 vccd1 vssd1",
               ],

But then because there is only one line (I guess) or because of spaces, it get split into a lits of words and then for some reason the first one end up with single quotes around it in the TCL which completely screws it and doesn't match ...

Review Class Structure and Ensure Consistency

OpenLane 2 is not adequately sticking to its general immutability requirements, and OOP is not being utilized as well as it should. One example pointed out is returning a "State" object may shield a Step that forgot to update metrics when it should, instead of returning an explicit empty dictionary.

Yosys Config Params

I'm trying to synthesize modules with standard cells, I've set both SYNTH_ELABORATE_ONLY and SYNTH_READ_BLACKBOX_LIB to true to deal with standard cells as blackboxes, but I'm getting errors like this:
ERROR: Module \sky130_fd_sc_hd__dlclkp_1 referenced in module \BYTE' in cell \genblk1.CG is not part of the design. .

Attached are the logs, config params for Openlane and the yosys script that completes successfully for reference.

issue.zip

Crash of OL2

In our Docker container, the version OpenLane v2.0.0a16 causes this fail when tested on spm:

/foss/designs > openlane spm/config.json 
Traceback (most recent call last):
  File "/usr/local/bin/openlane", line 8, in <module>
    sys.exit(cli())
  File "/usr/local/lib/python3.10/dist-packages/click/core.py", line 1130, in __call__
    return self.main(*args, **kwargs)
  File "/usr/local/lib/python3.10/dist-packages/click/core.py", line 1055, in main
    rv = self.invoke(ctx)
  File "/usr/local/lib/python3.10/dist-packages/click/core.py", line 1404, in invoke
    return ctx.invoke(self.callback, **ctx.params)
  File "/usr/local/lib/python3.10/dist-packages/click/core.py", line 760, in invoke
    return __callback(*args, **kwargs)
  File "/usr/local/lib/python3.10/dist-packages/click/decorators.py", line 26, in new_func
    return f(get_current_context(), *args, **kwargs)
  File "/usr/local/lib/python3.10/dist-packages/openlane/__main__.py", line 421, in cli
    run(ctx, **run_kwargs)
  File "/usr/local/lib/python3.10/dist-packages/openlane/__main__.py", line 103, in run
    flow = TargetFlow.init_with_config(
  File "/usr/local/lib/python3.10/dist-packages/openlane/flows/flow.py", line 207, in init_with_config
    config_resolved, design_dir_resolved = ConfigBuilder.load(
  File "/usr/local/lib/python3.10/dist-packages/openlane/config/builder.py", line 217, in load
    loaded = loader(
  File "/usr/local/lib/python3.10/dist-packages/openlane/config/builder.py", line 238, in _loads
    return Self._load_dict(
  File "/usr/local/lib/python3.10/dist-packages/openlane/config/builder.py", line 278, in _load_dict
    config_in, pdkpath, scl = Self._get_pdk_config(
  File "/usr/local/lib/python3.10/dist-packages/openlane/config/builder.py", line 445, in _get_pdk_config
    config_in[Keys.scl] = scl
  File "/usr/local/lib/python3.10/dist-packages/openlane/config/config.py", line 159, in __setitem__
    raise AttributeError("Config objects are immutable.")
AttributeError: Config objects are immutable.

Dictionary Configuration Issue

Trying to build Config objects from dictionaries instead of Tcl/JSON files raises InvalidConfig due to design_dir not being properly assigned.

Should be fixed by #52.

Expressions don't work in python dict config

When using init_with_config using a python dict and not a json file, then _load_dict ends up being called without resolve_json=True argument and the user has no way to set it, which makes expressions don't work.

Hierarchical LVS

Add support for hierarchical LVS

Quoting @mo-hosni:

Instead of treating macros as black-box instances in GDS LVS, gate-level netlists for the macros may be used. This script might be usefull [sic]

GF180 Support

OpenLane 2 currently does not have verified functionality with GF180.

Support latest PDK

af3485525297d5cbe93c129ea853da2d588fac41 doesn't work with OpenLane 2 due to a change in one of the variable names.

Implement Sylvain's Diode Insertion Script

We've decided that only the following diode insertion strategies will be carried forward:

0 -> None
3 -> OpenROAD
4 -> Sylvain's Script
6 -> Sylvain's Script + OpenROAD

The OpenROAD flow is already implemented, so Sylvain's script must also be implemented behind a different flag. The four combinations of the two flags will enable these strategies.

KeyError: 'STD_CELL_LIBRARY' on default designs

Hi Donn! Hope you are well. Just logging this for posterity, whatever it is worth.

My environment is the default ICC-OSIC-TOOLS which is a mantained version of the Efabless FOSS-ASIC-TOOLS. I clone and pip install -e . this repository, and go into the designs/spm directory.

After running the python harden.py this error appears:

Traceback (most recent call last):
  File "/foss/designs/openlane2/designs/spm/harden.py", line 5, in <module>
    flow = Classic(
  File "/foss/designs/openlane2/openlane/flows/sequential.py", line 77, in __init__
    super().__init__(*args, **kwargs)
  File "/foss/designs/openlane2/openlane/flows/flow.py", line 152, in __init__
    config, design_dir = Config.load(
  File "/foss/designs/openlane2/openlane/config/config.py", line 327, in load
    loaded = loader(
  File "/foss/designs/openlane2/openlane/config/config.py", line 390, in _load_dict
    config_in, pdkpath, scl = Self._get_pdk_config(
  File "/foss/designs/openlane2/openlane/config/config.py", line 565, in _get_pdk_config
    scl = pdk_env["STD_CELL_LIBRARY"]
KeyError: 'STD_CELL_LIBRARY'

I think there are a few reasons for this.

If I were to add this into the configuration dictionary of the harden.pydefault design, say:

import os
from openlane import Flow

Classic = Flow.get("Classic")

flow = Classic(
    {
        "PDK": "sky130A",
        "STD_CELL_LIBRARY": os.environ["STD_CELL_LIBRARY"], # I know it is 'sky130_fd_sc_hd'
        "DESIGN_NAME": "spm",
        "VERILOG_FILES": ["./src/spm.v"],
        "CLOCK_PORT": "clk",
        "CLOCK_PERIOD": 10,
    },
    design_dir=".",
)

flow.start()

I still get the same error. Looking into the source code,

I can see STD_CELL_LIBRARY is set in the config.py interactive method and is passed as a parameter into:

config.py

  @classmethod
  def interactive(
      Self,
      DESIGN_NAME: str,
      PDK: str,
      STD_CELL_LIBRARY: Optional[str] = None,
      PDK_ROOT: Optional[str] = None,
      **kwargs,
  )
  ....
config_in, _, _ = Self._get_pdk_config(
      PDK,
      STD_CELL_LIBRARY,
      PDK_ROOT,
  )

What I have been able to notice through print statements, is that the Config.load() config_in parameter is properly set based on the dictionary input but the scl parameter is just propagated along

{'PDK': 'sky130A', 'STD_CELL_LIBRARY': 'sky130_fd_sc_hd', 'DESIGN_NAME': 'spm', 'VERILOG_FILES': ['./src/spm.v'], 'CLOCK_PORT': 'clk', 'CLOCK_PERIOD': 10}

So if I simply change the harden.py script to:

import os
from openlane import Flow

Classic = Flow.get("Classic")

flow = Classic(
    {
        "PDK": "sky130A",
        "STD_CELL_LIBRARY": os.environ["STD_CELL_LIBRARY"], # I know it is 'sky130_fd_sc_hd'
        "DESIGN_NAME": "spm",
        "VERILOG_FILES": ["./src/spm.v"],
        "CLOCK_PORT": "clk",
        "CLOCK_PERIOD": 10,
    },
    scl=os.environ["STD_CELL_LIBRARY"], # I know it is 'sky130_fd_sc_hd'
    design_dir=".",
)

flow.start()

It all works fine now! Do you indend the config dictionary " "STD_CELL_LIBRARY": os.environ["STD_CELL_LIBRARY"], # I know it is 'sky130_fd_sc_hd'" to still be valid or you want people to input it via the scl parameter?

I am going to propose a fix to the default examples in designs so that this does not happen to people migrating from OpenLanes1 to this version. I decided I will port my whole project into using this tools and I am happy to help develop relevant functionality too!

Cheers for making such great software!

Implement Caravel

To prove OpenLane 2's ability to implement complex designs, Caravel should be implemented using OpenLane 2.

Generate `tcl_reproductible` for steps that don't crash

It would be nice to be able to generate the same kind of tcl_reproductible directory even for steps that don't crash outright because it could still be that something goes wrong there.

For instance here I'm having an issue that crashes in detailled routing but it seems like the issue might be earlier in globalrouting that the DB gets corrupted or something even though it doesn't crash there. So it'd be nice if I could send the same kind of reproductible build artefact for the globalrouting step.

PDN Obstructions

Add the ability to create metal-layer obstructions before PDN generation.

Add testing CI

OpenLane 2 should test multiple designs before merge instead of a simple smoke test.

We should leverage our GCP resources to run as many designs as possible.

SYNTH_ELABORATE_ONLY doesn't do anything

This is pretty much a requirement for the user_project_wrapper.
In OpenLane 1 it would trigger a different yosys script but here, although the Variable exists, it doesn't do anything AFAICT.

Hierarchical STA, hierarchical LVS, and routing obstructions.

The following features would be very useful and can be added to openlane2.

  • Hierarchical STA:
    Instead of treating macros as black-box instances with liberty files in STA, gate-level netlists and spef files for the macros may be used. This script might be useful.
  • Hierarchical LVS:
    Instead of treating macros as black-box instances in GDS LVS, gate-level netlists for the macros may be used. This script might be usefull.
  • PDN and Placement Obstructions:
    Adding obstructions before PDN generation and before placement is useful in many cases.

Add synthesis checks and linting

OpenLane currently has improved checks on Synthesis as well as linting using Verilator. These should be ported to OL2.

Note: may involve Nix.

Dropping support for Tcl configuration

Suggested by @shalan


OpenLane 2 should not carry the legacy of Tcl as it greatly complicates the codebase.

Unfortunately, the PDK in its current state only includes Tcl configuration files. The PDK would thus need to be updated to drop them for a new config format (either Python or JSON, to be discussed.)

The problem with this is that this new format would not be compatible with OpenLane 1, while the Tcl import mechanism as it currently exists in OpenLane 2, messy as it is, allows this compatibility to continue.

Port write_powered_def (functionality/objective)

As of now caravel_upw is reported as lvs clean but it is not. vccd2 and vssd2 are not connected to mprj2. The reason it is being reported as clean is because the verilog netlist compared against the layout is generated by openroad. It is comparing a layout and a schematic/netlist both generated from openroad. Doing lvs this way will fail to catch lvs errors caused by bad pdn configuration.

write_powered_def proved to be useful as it parses a yosys netlist where (supposedly) all power connections are defined. If due to a misconfiguration or other reasons, openroad fails with some power connections, the openroad netlist will have such connections missing leading to misleading lvs results.

Add Macro Object

Now that OpenLane 2 supports proper configuration dictionaries, Macro definitions should be an object, not a series of disjointed variables.

Macro orientation FN and FS not supported

Although I can see why W / E are not supported (because it would misalign PDN), the FN and FS orientation should be perfectly fine.

Just adding them to the list seems to work as expected looking at the resulting DEF

diff --git a/openlane/config/macro.py b/openlane/config/macro.py
index ba51ef0..ca9abe5 100644
--- a/openlane/config/macro.py
+++ b/openlane/config/macro.py
@@ -15,7 +15,7 @@ class Instance:
     """
 
     location: Tuple[Decimal, Decimal]
-    orientation: Union[Literal["N"], Literal["S"]]
+    orientation: Union[Literal["N"], Literal["S"], Literal["FN"], Literal["FS"]]
 
 
 @dataclass

Remote Execution

Add support for remote execution. This feature is essential for closed source PDKs and commercial EDA tools usage.

List of unused OpenROAD APIs

Manually created at 29-Jan 2023, through inspecting openlane and openroad source code

report_floating_nets
repair_timing -repair_tns
The worst setup path is always repaired. Next, violating paths to endpoints are
repaired to reduced the total negative slack. The percentage of violating
endpoints to repair is specified with -repair_tns is the percentage of
violating endpoints to repair (0 to 100). When tns_end_percent is zero (the
default), only the worst endpoint is repaired. When tns_end_percent is 100, all
violating endpoints are repaired. # inconcistent with seen behavior

tapcell -tap_prefix -endcap_prefix -*_master
cut_rows [-endcap_master endcap_master]
         [-halo_width_x halo_x]
         [-halo_width_y halo_y]
tapcell_ripup -tap_prefix -endcap_prefix

define_pin_shape_pattern {[-layer layer] \
    [-x_step x_step] \
    [-y_step y_step] \
    [-region region] \
    [-size size] \
    [-pin_keepout dist]}

set_io_pin_constraint -direction <direction>
                      -pin_names <names>
                      -region <edge:interval>

The `-direction` argument is the pin direction (input, output, inout, or
feedthrough). The `-pin_names` argument is a list of names. The `-region`
syntax is the same as that of the `-exclude` syntax.

The `-mirrored_pins` argument is a list of pins that sets pairs of pins
that will be symmetrically placed in the vertical or the horizontal edges.
The number of pins in this list must be even. For example, in
`set_io_pin_constraint -mirrored_pins {pin1 pin2 pin3 pin4 pin5 pin6}`,
the pins `pin1` and `pin2` will be placed symmetrically to each other.
Same for `pin3` and `pin4`, and for `pin5` and `pin6`.

place_pin [-pin_name <pin_name>]
          [-layer <layer>]
          [-location <{x y}>]
          [-pin_size <{width height}>]

place_pins [-hor_layers <h_layers>] # multiple
           [-ver_layers <v_layers>] # multiple
           [-random_seed <seed>]
           [-exclude <interval>]
           [-group_pins <pins>] Specify a list of pins to be placed together on the
           [-corner_avoidance <length>] Specify the distance (in microns) from
    each corner within which pin placement should be avoided.
           [-min_distance <distance>]
           [-min_distance_in_tracks]

define_power_switch_cell -name <name> \
                         -control <control_pin_name> \
                         [-acknowledge <acknowledge_pin_name>] \
                         -switched_power <switched_power_pin> \
                         -power <unswitched_power_pin> \
                         -ground <ground_pin>

define_pdn_grid [-obstructions <list_of_layers>]
    Specify the layers to add routing blockages, in order to avoid DRC violations

define_pdn_grid -macro \
                [-grid_over_pg_pins|-grid_over_boundary] \
                [-orient <list_of_valid_orientations>] \
                [-instances <list_of_instances] \
                [-cells <list_of_cells>] \
                [-obstructions <list_of_layers>]

| `-grid_over_boundary` | Place the power grid over the entire macro. |
| `-grid_over_pg_pins` | Place the power grid over the power ground pins of the macro. (Default) |
| `-instances` | For a macro, defines a set of valid instances. Macros with a matching instance name will use this grid specification. |
| `-cells` | For a macro, defines a set of valid cells. Macros which are instances of one of these cells will use this grid specification. |
| `-orient` | For a macro, defines a set of valid orientations. LEF orientations (N, FN, S, FS, E, FE, W and FW) can be used as well as standard geometry orientations (R0, R90, R180, R270, MX, MY, MXR90 and MYR90). Macros with one of the valid orientations will use this grid specification. |
| `-obstructions` | Specify the layers to add routing blockages, in order to avoid DRC violations |

define_pdn_grid -existing

define_pdn_grid [-name <name>] \
                [-switch_cell <power_switch_cell_name> ] \
                [-power_control <power_constrol_signal_name>] \
                [-power_control_network (STAR|DAISY)]

add_pdn_stripe  [-extend_to_boundary] \
                [-snap_to_grid] \
                [-number_of_straps count] \
                [-nets list_of_nets]
| `-extend_to_boundary` | Extend the stripes to the boundary of the grid |
| `-snap_to_grid` | Snap the stripes to the defined routing grid |
| `-number_of_straps` | Number of power/ground pairs to add |
| `-nets` | Limit straps to just this list of nets |

add_pdn_ring [-pad_offset offset_value] \
             [-add_connect] \
             [-extend_to_boundary] \
             [-connect_to_pads] \
             [-connect_to_pad_layers layers] \
             [-nets list_of_nets]

| `-pad_offset` | When defining a power grid for the top level of an SoC, can be used to define the offset of ring from the pad cells |
| `-add_connect` | Automatically add a connection between the two layers |
| `-extend_to_boundary` | Extend the rings to the grid boundary |
| `-connect_to_pads` | The core side of the pad pins will be connected to the ring |
| `-connect_to_pad_layers` | Restrict the pad pins layers to this list |
| `-nets` | Limit straps to just this list of nets |

add_pdn_connect [-cut_pitch pitch_value] \
                [-fixed_vias list_of_fixed_vias] \
                [-dont_use_vias list_of_vias] \
                [-max_rows rows] \
                [-max_columns columns] \
                [-ongrid ongrid_layers] \
                [-split_cuts split_cuts_mapping]

| `-cut_pitch` | When the two layers are parallel e.g. overlapping stdcell rails, specify the distance between via cuts |
| `-fixed_vias` | List of fixed vias to be used to form the via stack |
| `-dont_use_vias` | List or pattern of vias to not use to form the via stack |
| `-max_rows` | Maximum number of rows when adding arrays of vias |
| `-max_columns` | Maximum number of columns when adding arrays of vias |
| `-ongrid` | List of intermediate layers in a via stack to snap onto a routing grid |
| `-split_cuts` | Specifies layers to use split cuts on with an associated pitch, for example `{metal3 0.380 metal5 0.500}`. |

pdngen [-dont_add_pins] \
       [-reset] \
       [-ripup] \
       [-report_only] \
       [-failed_via_report file]

| `-dont_add_pins` | Prevent the creation of block pins during |
| `-reset` | Reset the grid and domain specifications |
| `-ripup` | Ripup the existing power grid, as specified by the voltage domains |
| `-report_only` | Print the current specifications |
| `-failed_via_report` | Generate a report file which can be viewed in the DRC viewer for all the failed vias (ie. those that did not get built or were removed). |

repair_pdn_vias [-all] \
                [-net net_name]

To remove vias which generate DRC violations after detailed placement and routing use `repair_pdn_vias`.


global_placement
    [-incremental]
    [-bin_grid_count grid_count] # forced value - basic placement
    [-init_density_penalty init_density_penalty] # forced value - basic placement
    [-init_wirelength_coef init_wirelength_coef]
    [-min_phi_coef min_phi_conef]
    [-max_phi_coef max_phi_coef]
    [-overflow overflow]a # forced value - basic placement
    [-initial_place_max_iter initial_place_max_iter] # forced value - basic placement
    [-initial_place_max_fanout initial_place_max_fanout]
    [-routability_check_overflow routability_check_overflow]
    [-routability_max_density routability_max_density]
    [-routability_max_bloat_iter routability_max_bloat_iter]
    [-routability_max_inflation_iter routability_max_inflation_iter]
    [-routability_target_rc_metric routability_target_rc_metric]
    [-routability_inflation_ratio_coef routability_inflation_ratio_coef]
    [-routability_pitch_scale routability_pitch_scale]
    [-routability_max_inflation_ratio routability_max_inflation_ratio]
    [-routability_rc_coefficients routability_rc_coefficients]
    [-timing_driven_net_reweight_overflow]
    [-timing_driven_net_weight_max] *
    [-timing_driven_nets_percentage] *
    [-verbose_level level] *
    [-force_cpu] 

- `-skip_initial_place` : Skip the initial placement (BiCGSTAB solving) before Nesterov placement. IP improves HPWL by ~5% on large designs. Equal to '-initial_place_max_iter 0'
- `-incremental` : Enable the incremental global placement. Users would need to tune other parameters (e.g., init_density_penalty) with pre-placed solutions.
- `-bin_grid_count`: set bin grid's counts. Default value is defined by internal heuristic. Allowed values are  `[64,128,256,512,..., int]`.
- `-init_density_penalty`: set initial density penalty. Default value is 8e-5. Allowed values are `[1e-6 - 1e6, float]`.
- `-init_wirelength_coef`: set initial wirelength coefficient. Default value is 0.25. Allowed values are `[unlimited, float]`.
- `-min_phi_coef`: set `pcof_min(µ_k Lower Bound)`. Default value is 0.95. Allowed values are `[0.95-1.05, float]`.
- `-max_phi_coef`: set `pcof_max(µ_k Upper Bound)`. Default value is 1.05. Allowed values are `[1.00-1.20, float]`.
- `-overflow`: set target overflow for termination condition. Default value is 0.1. Allowed values are `[0-1, float]`.
- `-initial_place_max_iter`: set maximum iterations in initial place. Default value is 20. Allowed values are `[0-MAX_INT, int]`.
- `-initial_place_max_fanout`: set net escape condition in initial place when 'fanout >= initial_place_max_fanout'. Default value is 200. Allowed values are `[1-MAX_INT, int]`.
- `-timing_driven_net_reweight_overflow`: set overflow threshold for timing-driven net reweighting. Allowed values are `tcl list of [0-100, int]`.
- `-timing_driven_net_weight_max`: Set the multiplier for the most timing critical nets. Default value is 1.9.
- `-timing_driven_nets_percentage`: Set the percentage of nets that are reweighted in timing-driven mode. Default value is 10. Allowed values are `[0-100, float]`
- `-verbose_level`: set verbose level for RePlAce. Default value is 1. Allowed values are `[0-5, int]`.
- `-force_cpu`: Force to use the CPU solver even if the GPU is available.


macro_placement [-halo {halo_x halo_y}]
                [-channel {channel_x channel_y}]
                [-fence_region {lx ly ux uy}]
                [-snap_layer snap_layer_number]

-   -halo horizontal/vertical halo around macros (microns)
-   -channel horizontal/vertical channel width between macros (microns)
-   -fence_region - restrict macro placements to a region (microns). Defaults to the core area.
-   -snap_layer_number - snap macro origins to this routing layer track

set_placement_padding -global|-instances insts|-masters masters # use -instances for diode_padding ?
                      [-left pad_left] [-right pad_right]

configure_cts_characterization
                               [-slew_steps <slew_steps>] \
                               [-cap_steps <cap_steps>]

-   `-slew_steps` is the number of steps that max_slew will be divided into
    for characterization. If this parameter is omitted, the default is
    12.
-   `-cap_steps` is the number of steps that max_cap will be divided into
    for characterization. If this parameter is omitted, the default is 34.

clock_tree_synthesis {[-wire_unit unit]
                     [-buf_list buflist] \
                     [-root_buf buf] \
                     [-clk_nets nets] \
                     [-tree_buf buf] \
                     [-branching_point_buffers_distance] \
                     [-clustering_exponent] \
                     [-clustering_unbalance_ratio] \
                     [-sink_clustering_size] \
                     [-sink_clustering_max_diameter] \
                     [-sink_clustering_enable] \
                     [-balance_levels] \
                     [-sink_clustering_levels levels] \
                     [-num_static_layers] \
                     [-sink_clustering_buffer] \
                    }

-   `-wire_unit` is the minimum unit distance between buffers for a specific
    wire. If this parameter is omitted, the code gets the value from ten times
    the height of `-root_buffer`.
-   `-branching_point_buffers_distance` is the distance (in micron) that
    a branch has to have in order for a buffer to be inserted on a branch
    end-point. This requires the `-distance_between_buffers` value to be set.
-   `-clustering_exponent` is a value that determines the power used on the
    difference between sink and means on the CKMeans clustering algorithm. If
    this parameter is omitted, the code gets the default value (4).
-   `-clustering_unbalance_ratio` is a value that determines the maximum
    capacity of each cluster during CKMeans. A value of 50% means that each
    cluster will have exactly half of all sinks for a specific region (half for
    each branch). If this parameter is omitted, the code gets the default value
    (0.6).


set_global_routing_region_adjustment {lower_left_x lower_left_y upper_right_x upper_right_y}
                                     -layer layer -adjustment adjustment

set_pin_offset # groute

set_global_routing_random [-seed seed]
                          [-capacities_perturbation_percentage percent]
                          [-perturbation_amount value]

The `set_global_routing_random` command enables randomization of
global routing results. The randomized global routing shuffles the
order of the nets and randomly subtracts or adds to the capacities of
a random set of edges.  The `-seed` option sets the random seed.  A
non-zero seed enables randomization. The


global_route {[-guide_file out_file] \
                                  [-congestion_iterations iterations] \
                                  [-congestion_report_file file_name] \
                                  [-grid_origin origin] \
                                  [-overflow_iterations iterations] \
                                  [-critical_nets_percentage percent] \
                                  [-allow_overflow] \
                                  [-verbose]

-   `grid_origin`: Set the (x, y) origin of the routing grid in DBU. For
    example, `-grid_origin {1 1}` corresponds to the die (0, 0) + 1 DBU in each
    x-, y- direction.
-   `congestion_report_file`: Set the file name to save congestion report. The
-   `critical_nets_percentage`: Set the percentage of nets with the worst slack value that are considered timing critical, having preference over other nets during congestion iterations (e.g. `-critical_nets_percentage 30`). The default percentage is 0%.


repair_antennas
                [-ratio_margin margin]
Use `-ratio_margin` to add a margin
to the antenna ratios. `-ratio_margin` is between 0 and 100.


report_wire_length [-net net_list]
                   [-file file]
                   [-global_route]
                   [-detailed_route]
                   [-verbose]
                   # tried it once - the report suppressed the rest of the warnings

detailed_route
    [-output_cmap filename]
    [-output_guide_coverage filename]
    [-db_process_node name]
    [-disable_via_gen]
    [-droute_end_iter iter]
    [-via_in_pin_bottom_layer layer]
    [-via_in_pin_top_layer layer]
    [-or_seed seed] # hardcoded
    [-or_k_ k]
    [-verbose level] # hardcoded
    [-param filename]
    [-distributed]
    [-remote_host rhost]
    [-remote_port rport]
    [-shared_volume vol]
    [-cloud_size sz]
    [-clean_patches]
    [-no_pin_access]
    [-min_access_points count]
    [-save_guide_updates]
    [-repair_pdn_vias layer]

buffer_ports [-max_utilization util]
commands stop when the design area is `-max_utilization util` percent of the core area

repair_clock_inverters
report_floating_nets
report_long_wires

extract_parasitics
  [-corner_cnt count]             process corner count
  [-max_res ohms]                 combine resistors in series up to
                                  <max_res> value in OHMS
  [-coupling_threshold fF]        coupling below the threshold is grounded
  [-lef_res]                      use per-unit RC defined in LEF
  [-cc_model track]               calculate coupling within
                                  <cc_model> distance
  [-context_depth depth]          calculate upper/lower coupling from
                                  <depth> level away
  [-no_merge_via_res]             separate via resistance

DFT?
improve_placement # undocumented

sta::define_cmd_args "run_worker" {
    [-host host]
    [-port port]
    [-i]
}
sta::define_cmd_args "run_load_balancer" {
    [-host host]
    [-port port]
    [-workers_domain workers_domain]
}
sta::define_cmd_args "add_worker_address" {
    [-host host]
    [-port port]
}

density_fill -rules <json_file> [-area <list of lx ly ux uy>]

PartitionMgr: is a tool that performs partitioning/clustering on a specific netlist.
It provides a wrapper of three well-known permissively
open-sourced tools: Chaco, GPMetis and MLPart.

Restructure: is an interface to ABC for local resynthesis. The package allows
logic restructuring that targets area or timing. It extracts a cloud of logic
using the OpenSTA timing engine, and passes it to ABC through blif interface.
Multiple recipes for area or timing are run to obtain multiple structures from
ABC; the most desirable among these is used to improve the netlist. The ABC
output is read back by a blif reader which is integrated to OpenDB. blif writer
and reader also support constants from and to OpenDB. Reading back of constants
requires insertion of tie cells which should be provided by the user as per the
interface described below.

restructure -liberty_file <liberty_file>
            -target "area"
            -tielo_pin  <tielo_pin_name>
            -tiehi_pin  <tiehi_pin_name>
restructure -liberty_file <liberty_file>
            -target "delay"
            -slack_threshold <slack_val>
            -depth_threshold <depth_threshold>
            -tielo_pin  <tielo_pin_name>
            -tiehi_pin  <tiehi_pin_name>

write_abstract_lef (-bloat_factor bloat_factor|-bloat_occupied_layers) \
		   filename
write_lef
write_cdl {[-include_fillers]
    -masters masters_filenames out_filename }
assign_ndr { -ndr name (-net name | -all_clocks) }
report_global_connect *
drt::check_drc

SYNTH_READ_BLACKBOX_LIB broken

Enabling SYNTH_READ_BLACKBOX_LIB makes the flow fail early because the yosys script don't expect the new "dictionary" LIB variable.

Typo in check antenna script name

The script file is named check_antennae.tcl but in openlane/steps/openroad.py, it's called check_antennas.tcl.
( e vs s at the end ).

Running smoke test as the very first command fails because the PDK_ROOT dir is created as root:root

When launching it from scratch on a brand new system, the PDK_ROOT dir not created yet, it will be created but as belonging to root:root event though I'm running openlane as normal user (not even sure how/why ... I'm assuming through some docker magic or something), and then them volare try to do the actual install ... wel it can't write to it as normal user so it fails with a permission error.

`PDN_CFG` is not supported

The code to support it in the TCL is there but it's missing from the pdn_variables in openlane/steps/common_variables.py.

Adding it seems to do the trick.

diff --git a/openlane/steps/common_variables.py b/openlane/steps/common_variables.py
index 88b31ed..ec43275 100644
--- a/openlane/steps/common_variables.py
+++ b/openlane/steps/common_variables.py
@@ -138,6 +138,11 @@ pdn_variables = [
         "Controls the layers used in the power grid. Depending on whether the design is the core of a chip or a macro inside the core.",
         default=True,
     ),
+    Variable(
+        "PDN_CFG",
+        Optional[str],
+        "Custom PDN config",
+    ),
 ]
 
 routing_layer_variables = [

Docker smoke test does not terminate cleanly on macOS

When Docker terminates and OpenLane tries to clean up, this happens:

  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 846, in onerror
    cls._rmtree(path, ignore_errors=ignore_errors)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 855, in _rmtree
    _shutil.rmtree(name, onerror=onerror)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/shutil.py", line 731, in rmtree
    onerror(os.rmdir, path, sys.exc_info())
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 840, in onerror
    resetperms(path)
  File "/nix/store/akdd66048jfpl6p0k4414i3yh8ybrq52-python3-3.10.9/lib/python3.10/tempfile.py", line 832, in resetperms
    _os.chflags(path, 0)
RecursionError: maximum recursion depth exceeded while calling a Python object

This is amazingly due to Docker keeping some kind of a handle on the mounted volume for a little bit longer than the container is alive.

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