yosyshq Goto Github PK
Name: Yosys Headquarters
Type: Organization
Bio: Yosys Open SYnthesis Suite
Blog: http://yosyshq.net/
Name: Yosys Headquarters
Type: Organization
Bio: Yosys Open SYnthesis Suite
Blog: http://yosyshq.net/
ABC: System for Sequential Logic Synthesis and Formal Verification
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
Place and route tool for FPGAs
Equivalence checking with Yosys
Multi-platform nightly builds of open source FPGA tools
A clean customizable documentation theme for Sphinx
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
Modular Application Utilities
Mutation Cover with Yosys (MCY)
Naive Educational RISC V processor
nextpnr portable FPGA place and route tool
Benchmarks for nextpnr
Multi-platform nightly builds of open source digital design and verification tools
A padring generator for ASICs
PicoRV32 - A Size-Optimized RISC-V CPU
Documenting the Lattice ECP5 bit-stream format.
Project Trellis database
pyosys tests
RISC-V Formal Verification Framework
SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
GUI for SymbiYosys
Sequence of Covers with Yosys
Set up your GitHub Actions workflow with a OSS CAD Suite
Yosys syntax highlighter for the Sublime Text 3 editor
A Verilog Synthesis Regression Test
Yosys Open SYnthesis Suite
Benchmarks for Yosys development
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