Topic: vitis Goto Github
Some thing interesting about vitis
Some thing interesting about vitis
vitis,A Comprehensive Dataflow Compiler for High-Level Synthesis
Organization: anydsl
vitis,A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
User: aryan-programmer
vitis,Flexible Linear Algebra with Matrix-Empowered Synthesis (for Vitis HLS)
Organization: autohdw
Home Page: https://flames.autohdw.com
vitis,This repo explain how to setup and install Vitis IDE for acceleration projects
User: bassam-kobasy
vitis,Learn how to get started with BeetleboxCI and Vitis Unified Development Environment with this tutorial covering using computer vision on FPGA technology
Organization: beetleboxorg
vitis,System based on hardware (FPGA) and software to implement MD5 Cryptographic Hash Function
User: catarinaacsilva
vitis,A Scalable BFS Accelerator on FPGA-HBM Platform
Organization: cgcl-codes
vitis,A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
User: definelicht
vitis,This is my sandbox for experimenting with the features offered by the AMD (Xilinx) FreeRTOS port. The main platform used is the Digilent Zybo-z7-20. The implemented system is quite simple, comprising a range of GPIO features (LEDs, buttons, switches, and test outputs for monitoring) and two UART communication channels.
User: der-mur
vitis,Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
User: dsa-shua
vitis,A TFTP server running on Zynq-7000
User: efetunca
vitis,High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
User: federicoserafini
vitis,3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
User: florin623
vitis,100 Gbps TCP/IP stack for Vitis shells
Organization: fpgasystems
Home Page: https://systems.ethz.ch/fpga
vitis,An end-to-end GCN inference accelerator written in HLS
User: jasonlin316
vitis,HLS & hls4ml Tutorial
User: jmduarte
Home Page: https://fastmachinelearning.org/
vitis,Reconfigurable Systems on Chip Mini Project
User: joseamador95
vitis,Vitis 2020.1 Acceleration Examples and Developed Large Size Matrix Multiplication Examples
User: kaanolgu
vitis,Efficient Algorithm Level Error Detection for Number-Theoretic Transform
User: kasraahmadi
vitis,Error detection enabled tau-NAF conversion on Koblitz Curves
User: kasraahmadi
vitis,Error detection enabled Window method scalar multiplication on Elliptic Curves
User: kasraahmadi
vitis,Implementation of an IEEE 802.11p PHY realitime receiver in VHDL on ZedBoard and ADRV9002. Master's thesis at CTU in Prague FEE.
User: michaelkimmer
Home Page: http://hdl.handle.net/10467/114801
vitis,A Hardware-based Keylogging User Authentication System using a Zybo Z7 or Raspberry Pi
User: michealcarac
vitis,Construct and Analyze the North American Vitis pangenome
User: noecochetel
vitis,Notes on the Eclypse Z7 development board
User: pavel-demin
Home Page: https://pavel-demin.github.io/eclypse-z7-notes/
vitis,Notes on the Red Pitaya Open Source Instrument
User: pavel-demin
Home Page: http://pavel-demin.github.io/red-pitaya-notes/
vitis,Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
User: ribesstefano
vitis,In this project I wanted to implement a microprocessor on an FPGA with the ability to write files onto an SD card (micro SD in particular) exploiting the Arty A7 development board and the Digilent PModSD.
User: riccardonicolaidis
vitis,Creating a Custom IP for PS-PL data exchange in Vivado
User: rogermiranda1000
vitis,The code repository of DGCNN on FPGA: Acceleration of The Point Cloud Classifier Using FPGAs
User: salehjg
vitis,The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/
User: sinakarvandi
Home Page: https://rayanfam.com/topics/hardware-design-stack/
vitis,FPGA acceleration of arbitrary precision floating point computations.
Organization: spcl
vitis,Ultra96 (v1) projects for Vitis platform
User: t-kuha
vitis,CyDAQ DSP Platform Firmware and Software Redesign - Iowa State University Senior Design May 2023 Group 47 - Blake Fisher, Cole Langner, Corbin Kems, Jens Rasmussen, Long Zeng, Wyatt Duberstein, Yohan Bopearatchy
User: wyattduber
Home Page: https://sdmay23-47.sd.ece.iastate.edu/
vitis,Vitis In-Depth Tutorials
Organization: xilinx
Home Page: https://Xilinx.github.io/Vitis-Tutorials/
vitis,Vitis_Accel_Examples
Organization: xilinx
Home Page: http://xilinx.github.io/Vitis_Accel_Examples/
vitis,Run Time for AIE and FPGA based platforms
Organization: xilinx
Home Page: https://xilinx.github.io/XRT
vitis,Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
Organization: xilinx
Home Page: https://xilinx.github.io/xup_compute_acceleration/
vitis,VNx: Vitis Network Examples
Organization: xilinx
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