Time-Card/OSC/HW/SA45 Daughtercard/Latest)/SCH_SA45_DaughterCard.pdf

does not connect the BITE output (SA45) or "Lock Indication" (IQP_ICPT1) to the LOCK pin (P6).

Maybe its obvious to those with more experience, but I'm sure what software I would need to look at the schematic source files. Would be helpful to add to the README.

I've heard that Google's Spanner has improved performance a lot because of The Atomic Clock. So I'm not sure if this can be applied in blockchain, like the more precise TIMESTAMP, or improving transaction throughput of blockchain.
You are the developer of TIME CARD,can you give me some advices about the other application scenarios. I am looking forward to your reply.

As the title says, I'm curious what these sensors are used for in a time measurement device, furthermore because they don't seem to be mentioned anywhere outside of the ECAD.

Q1:Now I 'm using the PCB of Beta-V1. By comparing Prototype-V0, I found that you delete the mirco&mini USB UART. Does this mean that PCIE interface is instead of the UART? So when I use the UCM under the WINDOWS system，I just plug in the motherboard?

Q2:In Time-Card\SOM\FPGA\Binaries , what are the differences among these files? what are they used for?

Is the DRAM on the AC7100B SoM board used in Timing Card operation?

File: OCP Receiver Carrier Board Form Factor (In Progress).docx

The SMB connector on the F9T-RCB needs to be dimensioned. X, Y, and Z of the center (signal) pin should be shown.

The D11(LED) has been blinkling，What does it mean. By the way，i have been using crystal oscillator.
Thx.

What are the pin assignments for the "Version: 0x8003 (Production Version)" FPGA?

They aren't in "Readme_Production.pdf".

The driver loads but fails to allocate interrupts when connecting the TimeCard to the RPi CM4 2GB and 4GB modules.
As a result, no TTY ports are present.
The same card works properly in the x86 platform.
Tested on the in-tree 5.19.0 driver.

[    4.278190] ptp_ocp 0000:03:00.0: enabling device (0000 -> 0002)
[    4.279502] ptp_ocp 0000:03:00.0: irq 1 out of range, skipping ts0
[    4.279531] ptp_ocp 0000:03:00.0: irq 2 out of range, skipping ts1
[    4.279546] ptp_ocp 0000:03:00.0: irq 6 out of range, skipping ts2
[    4.279559] ptp_ocp 0000:03:00.0: irq 15 out of range, skipping ts3
[    4.279572] ptp_ocp 0000:03:00.0: irq 16 out of range, skipping ts4
[    4.279693] ptp_ocp 0000:03:00.0: irq 11 out of range, skipping signal_out[0]
[    4.279708] ptp_ocp 0000:03:00.0: irq 12 out of range, skipping signal_out[1]
[    4.279721] ptp_ocp 0000:03:00.0: irq 13 out of range, skipping signal_out[2]
[    4.279733] ptp_ocp 0000:03:00.0: irq 14 out of range, skipping signal_out[3]
[    4.280026] ptp_ocp 0000:03:00.0: irq 7 out of range, skipping i2c_ctrl
[    4.280040] ptp_ocp 0000:03:00.0: irq 3 out of range, skipping gnss_port
[    4.280052] ptp_ocp 0000:03:00.0: irq 4 out of range, skipping gnss2_port
[    4.280064] ptp_ocp 0000:03:00.0: irq 5 out of range, skipping mac_port
[    4.280077] ptp_ocp 0000:03:00.0: irq 10 out of range, skipping nmea_port
[    4.280089] ptp_ocp 0000:03:00.0: irq 9 out of range, skipping spi_flash
[    4.359245] ptp_ocp 0000:03:00.0: Version 1.2.0, clock PPS, device ptp1
[    4.359297] ptp_ocp 0000:03:00.0: Time: 1660295049.472829090, in-sync

The CM4s' datasheet states that the module should be able to allocate up to 32 vectors, and the lspci confirms it:

03:00.0 Memory controller: Facebook, Inc. Device 0400
        Subsystem: Xilinx Corporation Device 0007
        Flags: bus master, fast devsel, latency 0, IRQ 39
        Memory at 600000000 (32-bit, non-prefetchable) [size=32M]
        Capabilities: [40] Power Management version 3
        Capabilities: [48] MSI: Enable+ Count=1/32 Maskable- 64bit+
        Capabilities: [60] Express Endpoint, MSI 00
        Capabilities: [100] Device Serial Number 00-00-00-00-00-00-00-00
        Kernel driver in use: ptp_ocp
        Kernel modules: ptp_ocp

BOM

• item 41 (DS3231 RTC) shows "U5" as ref des. schematic shows "U3A"

• item 40 (1x3 header) does not have corresponding jumpers

• item 29 (IC REG BUCK ADJUSTABLE 2A 8SOIC). Data sheet says this part is not recommended for new designs (add 210817)

• no BOM item for CSAC and SA.3x/SA.5x

• no BOM item for U11 (sch. p.6,A2; assume SiT5721)

• no BOM item for U13 (sch. p.6,B4; assume SiT5356)

• no BOM item for U4 (sch. p.5,C5; BMP388. Note: this part is not recommended for new designs)

• no BOM item for U7 (sch. p.5,D5; AT24MAC402-STUM-T)

SCHEMATIC

• p. 6,C2

  MAC devices SA.3x and SA.5x are labeled "RV-3049-C3"

  Need notation: "Install one of CSAC, SA.3x, or SA.5x".

  Assuming connector U10B would interfere with installation of the CSAC or
  SA.3x oscillators, need notation: "Install U10B (connector) only if using SA.5x oscillator."

The nets MAC_10Mout, MAC_10Mout, MAC_RF_OUT, and MAC_FREQ_CTL are all shorted, as are MAC_PPSout and MAC_PPS_OUT+, and MAC_PPSin and MAC_PPSIN0+. This is probably related to the oscillator stuffing options as well.

The output dotting should only be on p. 6 where the oscillators are drawn and not on p. 7 at the connector. There should be a note clarifying the operation under the alternative stuffing options (including R17, the zero ohm resistor to GPS_TP1).

After installing Vivado 2019.1 and cloning the time card repository to my local machine, the script "CreateBinariesAll.tcl" fails with this error:

ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source: 
/TC_PpsSlave_1/SysClk_ClkIn
/TC_PpsSlave_1/SysClkNx_ClkIn

ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design C:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source/Implementation/Xilinx/TimeCard/TimeCard/TimeCard.srcs/sources_1/bd/TimeCard/TimeCard.bd 
ERROR: [Vivado 12-4756] Launch of runs aborted due to earlier errors while preparing sub-designs for run execution.

    while executing
"source "$ScriptFolder/CreateBinariesGolden.tcl""
    (file "C:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source/Implementation/Xilinx/TimeCard/CreateBinariesAll.tcl" line 28)

There are warnings in the Tcl console during "CreateProject.tcl", the first of which is:

## create_root_design ""
INFO: [IP_Flow 19-5107] Inferred bus interface 'ClkIn0_ClkIn' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ClkIn1_ClkIn' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'ClkIn0_ClkIn': ASSOCIATED_BUSIF bus parameter is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'ClkIn1_ClkIn': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source'.
WARNING: [IP_Flow 19-3656] If you move the project, the path for repository 'c:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source' may become invalid. A better location for the repository would be in a path adjacent to the project. (Current project location is 'c:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source/Implementation/Xilinx/TimeCard/TimeCard'.)
WARNING: [BD 41-1731] Type mismatch between connected pins: /BufgMux_IPI_0/ClkOut_ClkOut(undef) and /BufgMux_IPI_2/ClkIn0_ClkIn(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /BufgMux_IPI_1/ClkOut_ClkOut(undef) and /BufgMux_IPI_2/ClkIn1_ClkIn(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /BufgMux_IPI_2/ClkOut_ClkOut(undef) and /clk_wiz_1/clk_in1(clk)
WARNING: [BD 41-1306] The connection to interface pin /util_ds_buf_1/IBUF_DS_N is being overridden by the user. This pin will not be connected as a part of interface connection CLK_IN_D
    (_repeats 25 times, different instances_)
WARNING: [BD 41-702] Propagation TCL tries to overwrite USER strength parameter S_AXI_SUPPORTS_NARROW_BURST(false) on '/axi_pcie_0' with propagated value(true). Command ignored

Subsequently, there are 63 of these warnings(same warning, different blocks and domains):

WARNING: [BD 41-927] Following properties on pin /BufgMux_IPI_0/ClkIn0_ClkIn have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=TimeCard_Mhz10ClkSma_ClkIn 

What is the core material?

Is there a fab drawing showing outline, hole, and key component dimensions?

Folowup of a discussion at the ISCPS

I saw that the UTC offset is represented as a seperate file.
But the adjtimex syscall allows you to get/set the offset already.
https://www.man7.org/linux/man-pages/man2/adjtimex.2.html

so the question is, are this two parameters synced and only a second way to obtain / set the offset or are this two separate values?

Best Regard
TuxCoder

Title block shows:

Cannot open file C:\Users\beta\Desktop\TimecardLogo\TIMECARD.jpg.
File does not exist.

Title block shows "*" for sheet number starting with third sheet.

The forward voltage drop of +1.2V seems excessive for simple isolation.

The NetTimeLogic Configuration Manager can only run under windows system.

Q4： Is there any command in linux system to switch PPS source from FPGA to GNSS or MAC?

"Time-Card/SOM/FPGA/TimeCard_FPGA.png" shows an extra GNSS receiver (UART and PPS connections) as well as an UART in the upper left that is not labelled. These don't appear on the SOM connector P1 of the current schematic ("Timingcard_PROJECT_SCHEMATICS_BETA_V1.pdf", p.7). This change is reflected in the FPGA binaries directory as well.

• Are they being resurrected from the initial design shown in "Time-Card/ECAD/Prototype-V0/Timingcard_PROJECT.pdf"?
• Or, are they simply no-connects on P1?
• Or, can we expect a new design with an FPGA replacing the AC7100 SOM? If so, when would that land?

The vertical hole centers are referenced to the top surface of the short bend section at the upper end of the bracket. This position, being on the outside of the bend, is not as well controlled as the bottom surface. The CEM and off-the-shelf brackets all use the bottom surface as a reference.

The horizontal hole centers are properly referenced to the inside of the bend of the ears.

Also, not specified are:

• the overall length of the bracket
• the tapered section on the lower end
• the widths and lengths of the mounting tabs
• the width of the stiffener opposite the mounting tabs

MAC_USB_PWR goes to connector P1B-B8 and thence to FPGA pin V8, IO_L14P_T2_SRCC_13, per the AC7100 schematics.

This is curious, since USB power is +5V and there is no +5 going to the FPGA. Also, what kind of IOH spec does that thing have?

Looking for more details on the IMU being used in this application.

Is it mainly for vibration detection with an accelerometer?
Is the magnetometer being used to measure the earth's magnetic fields and magnetic fields coming off other components?

thank you.

How feasible do you think the following is:

An external solution that enables my computer's (a Dell XPS for example) outgoing packets to be timestamped with a very accurate clock however as you know my stock NIC does not support hardware timestamping nor do I have a PCIe slot.

My proposal:

A NIC with hardware time stamping and built in rubidium oscillator connected to my laptop via USB

The outgoing packets are sent to the NIC to be accurately timestamped before being transmitted

More power could be supplied to the external setup by an additional 5v usb connection

Ideally the only thing the computer would need is downloadable drivers to alter the ptp handling of the computer.

It will require a method of detecting and compensating for changes in latency between the NIC and computer caused by for instance using a different length USB cables/setups.

I would really like to further this idea, if you could let me know what you think I would be very grateful.

The time reported in the $GPZDA NMEA message on the NMEA serial port is incorrect. It returns GPS time instead of UTC.

The upper part shows the G*ZDA message from the Time Card, while the lower - reported by the UBX module (on the UBX serial port)

$GPZDA,144310.00,09,08,2022,00,00*66
$GPZDA,144311.00,09,08,2022,00,00*67
$GPZDA,144312.00,09,08,2022,00,00*64
$GPZDA,144313.00,09,08,2022,00,00*65
$GPZDA,144314.00,09,08,2022,00,00*62
$GPZDA,144315.00,09,08,2022,00,00*63
$GPZDA,144316.00,09,08,2022,00,00*60
$GPZDA,144317.00,09,08,2022,00,00*61
$GPZDA,144318.00,09,08,2022,00,00*6E

───────────────────────────────────────────────────────────────────────────────────
NT����$GNZDA,144155.00,09,08,2022,00,00*7B
MT����$GNZDA,144156.00,09,08,2022,00,00*78
LT����$GNZDA,144157.00,09,08,2022,00,00*79
KT��s�$GNZDA,144158.00,09,08,2022,00,00*76
JT��^$GNZDA,144159.00,09,08,2022,00,00*77
IT��I$GNZDA,144200.00,09,08,2022,00,00*78
HT��3$GNZDA,144201.00,09,08,2022,00,00*79
GT��($GNZDA,144202.00,09,08,2022,00,00*7A
FT���   8$GNZDA,144203.00,09,08,2022,00,00*7B

Release the latest package with updated HW design for Timecard. Previous versions will be stashed in a separate directory with their respective FPGA firmware binaries. *NOTE: This is only for SOM based Timecards.

Update timecard repository to include:

• Rb based SOM Timecard with dual GNSS
• Cs based SOM Timecard with dual GNSS
• Segmentation of FPGA firmware images
• Update documentation

/Time-Card/OSC)/LOF Spec v01.docx sections 5.3.1 and 5.3.2 are incomplete (and one dimension is incorrect).

Assuming the Microchip Technology MAC-SA5x is the template, then the following drawing is closer to what is needed. Not sure about what you want to do with the mounting holes. I believe they are at:

-15.24 -21.34 (near pin 1)
-15.88 19.81 (near pin 3)
15.88 18.26 (near pin 4)
15.88 -18.26 (near pin 5)

Also, does Microchip need to be acknowledged for this contribution (or permission obtained)?

Ref: file "Timingcard_PROJECT.pdf", in Time-Card/HW/ECAD/Prototype-V7/ECADv7.7z

The new status LED driver, U6, on sheet 2 of the new schematic has pin 1 ("SDB") pulled to ground through a 100K resistor.

The data sheet description of this pin reads: "Shutdown the chip when pulled low". That would render the driver and LED's useless.

Also, the pulldown is bypass by a 0.1 uF cap. Why?

1. "Time-Card\SOM\FPGA\Readme.pdf" shows that ANT1 and ANT2 are input ports;
   However, "Time-Card\ECAD\Beta-V1\USER_IO.SchDoc" shows that ANT1 and ANT2 are output ports;
   Futhermore, i can only get 10MHz (from my crystal oscillator) on the 4th pin of the "U8"(NC7SZ125M5), and there is nothing output on all four SMA ports ".

Q1: Could you please explain the contradiction?

2. “Time-Card\GNSS\UBX\RCB-F9T\README.md" recommands me to program the GNSS module by the UBX U-Center, but the 9th generation GNSS is not supported for the function of programming by U-Center.

Q2: Is it necessary for me to only get PPS on timecard port?
Q3: Does the RCB-F9T blong to 9th generation GNSS ? If so, How can I resolve it？

Last but not least, all these problems are based on the fact that I did not plug in PCIe, but only the external 12V power supply.

Thank you so much !!!

Just want to know price for ordering on jlpcb.
Gerber files and BOM are present and loaded without problems, but no CPL. So can`t figure out resulting price.

The +3.3V step-down regulator on p. 2, C3 has a max current rating of 2 A, for 6.6 W power.

Since the PCIe connector allows for up to 9.9 W for a standard height x4 card, why is there a regulator for +3.3V on the Timing Card?

Time Card starts with a random frequency offset (around 5ppm).
It doesn't correct the frequency until it gets the GNSS lock.

The issue is shown in the video below. It shows two traces:

• yellow: 10MHz from a PTP source synchronized to the GNSS signal
• green: 10MHz output of the Time Card.

Timestamps:
0:00 - boot and enable gnss_sync monitor
1:35 - GNSS sync acquired
4:20 - pull-in begins
5:11 - biggest frequency drift
5:14 - lock acquired

Just before the lock, the frequency drifts to ~ -20 ppm!

If this behavior is unavoidable (i.e., saving the last corrections and applying them on boot), there should be an option to squelch 10MHz output until it gets the initial lock, as in the current state, it breaks the 4.6 ppm limits of SyncE while locking.

I'm trying to build the open source FPGA binaries following the video "How to build the open source FPGA design for the Time Card from scratch", linked in the FPGA "README.md" file.

The first step, cloning the repository, was successful. The "CreateProject.tcl" script in Vivado appears to fail. I'm using the latest version of Vivado:

Vivado v2022.2 (64-bit)
SW Build: 3671981 on Fri Oct 14 05:00:03 MDT 2022
IP Build: 3669848 on Fri Oct 14 08:30:02 MDT 2022

The TCL console shows:

start_gui
source C:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source/Implementation/Xilinx/TimeCard/CreateProject.tcl
# set ScriptFile [file normalize [info script]]
# set ScriptFolder [file dirname $ScriptFile]
# cd $ScriptFolder
# set origin_dir $ScriptFolder
# set orig_proj_dir "[file normalize "$origin_dir"]"
# set _xil_proj_name_ "TimeCard"
# create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a100tfgg484-1 -force
INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.
Current project path is 'C:/Users/wis1/Documents/tc/Time-Appliance-Project/Time-Card/FPGA/Open-Source/Implementation/Xilinx/TimeCard/TimeCard'
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'.
# set proj_dir [get_property directory [current_project]]
# set obj [current_project]
# set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
# set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
WARNING: [Common 17-599] Property 'dsa.accelerator_binary_content' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
# set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
WARNING: [Common 17-599] Property 'dsa.accelerator_binary_format' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
# set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
WARNING: [Common 17-599] Property 'dsa.description' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
# set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
WARNING: [Common 17-599] Property 'dsa.dr_bd_base_address' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
# set_property -name "dsa.emu_dir" -value "emu" -objects $obj
ERROR: [Common 17-142] Invalid property name 'dsa.emu_dir'.  Please use the 'list_property' command to find properties supported by the target 'project' object.

The Messages tab shows:

General Messages[IP_Flow 19-234] Refreshing IP repositories
[IP_Flow 19-1704] No user IP repositories specified
[IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2022.2/data/ip'.
[Common 17-599] Property 'dsa.accelerator_binary_content' is deprecated for object type 'project'. dsa.* properties have been deprecated, please use the corresponding platform.* properties.
[Common 17-142] Invalid property name 'dsa.emu_dir'.  Please use the 'list_property' command to find properties supported by the target 'project' object.

This is the statement in "CreateProject.tcl" (line 51) which appears to cause the problem:

set_property -name "dsa.emu_dir" -value "emu" -objects $obj

Other than loading Vivado 2019.4, used in the video, what can I modify to get this working?

It seems like a plug is needed to make the connection to the atomic clock, but this part is not in the BOM.

In the now-closed issue #11, the requirements for acceleration and pressure sensor were laid to the MAC-5x oscillator data sheet. However...

The MAC-SA5x data sheet (Microchip #DS00003348B, March 2021) only mentions temperature in terms of operating / non-operating range, and frequency drift:

• Operating Temperature –40˚C to +75˚C
• Temperature-induced frequency errors <5x10-11 Hz/Hz from –10˚C to +75˚C
• Non-Opera

ting (Storage & Transport): –55˚C to +100˚C

Shock and Vibration are only specified with respect to maintaining lock.

Altitude (pressure) is only mentioned as a maximum for operation and storage/transport.

Can anyone explain how oscillator performance can be compensated for environmental effects based on what the spec sheet is presenting?

If loss of lock from temperature or shock/vibration occurs, won't other environmental monitoring in a data center be able to report? If localized over-temperature is a concern, then perhaps only that should be measured.

Are there any other citations for these environment impacts that are relevant to this application?

Is there a reason that a mini USB connector (J3, p.3,C5) is used, vs. the micro USB on J4 (p.5,B6)?

The mini USB isn't very common and adds to BOM complexity.

Also, the micro USB connector shows as J4 on the schematic and J2 in the BOM.

fento -> femto

https://en.wikipedia.org/wiki/Femtosecond

1. I noticed that MAC your official recommend is SA53. Can I use some other MAC or OCXO ,TCXO which can offer 10MHZ frequency source? If possible，how to deal with the problem of pins which are mismatch with the PCB of Beta-V1. I just wanna to replace it with our company’s MAC

2. You opened source the implementation of FPGA then I imported the Vivado project. According the TC_SmaSelector IP CORE , I can configure the SMA input/ouput ports. If I change the configuration, does it means that I should regenerate the bitstream files? I think it is a bit of trouble. In /Time Appliance Project/Time Card/Usage, by using the LINUX command such as " echo OUT: MAC >> sma1" which can also configure the ports. Both of them are equivalent？？？

3. In /SOM/FPGA/TestApp/TestAPP.c, I can only read result form the register, how do I write data to the register?

Looking forward your reply, THX.

Why is +3.3V_CLEAN connected to VDDIO (pin 1) of the pressure sensor U4 (p. 5,B5)?

Similarly, why is +3.3V connected to VDD (pin 3) of the IMU U8 (p.5,C2)?

The PCIe clock has DC blocking capacitors. Is that correct?

Ref: Timingcard_SCHEMATICS_BETA_V1.pdf, p. 3,A4/A5.

I was trying to do some research on how to make some diy electronics that use PCIe, and after a fruitless search baring the slot's pinout, I ended up here, being the only relay active project using PCIe (not Mini PCIe). How exactly does this, on the electronic level, interface with PCIe? Is that something documented elsewhere? Is this something I should ask somewhere else?

What are the licensing or royalty arrangements for the FPGA intellectual property?

There appear to be six IP cores from NetTimeLogic in use.

Ref: "Time-Card/SOM/FPGA/Readme.pdf", section 2.4

• Step 1 says: "Connect the USB/UART to a host PC running Windows." What USB/UART is that?
• Step 4 says: "Change your configuration as you need it..." Aren't the NetTimeLogic cores already configured in the FPGA binaries?

You expose a /dev/ptpX device. The ptp stands for precision time protocol which is a network protocol. Normally /dev/ptpX are physical hardware clocks PHC of either a Ethernet PHY or Ethernet MAC. To make use of the timing card in a network one or better two Ethernet MACs/PHYs are missing, because all the precision is useless if we afterwards need to have phc2sys from timing catd's /dev/ptpX to the system cock and then sys2phc from the system clock to /dev/ptpY, the PHC in a NIC available in the system.

Wouldn't it be much more straight forward to have the MACs/PHYs already integrated in timing card? The FPGA is there, so why not use Xilinx Ethernet MAC IP and add one or two external PHYs and obviously connect the FPGA with the PCIe bus?

Having a /dev/ptpX device that is not connected to a MAC/PHY seems just not right to me.

https://hackaday.io/project/167202/instructions
Aweigh here was working on calculation current location using sun location. Of course reverse can be done using sun/moon... to calculate time.

GNSS can be spoofed or jammed. Local time calculated by sun/moon is a lot harder to jam and can be hard to spoof.

Back to basics of calibrating atomic clock straight from sun/moon. Yes using GNSS when the signal is good to work out what the local offsets are.

Its just that thing I got thinking this has added atomic clock to fix the issue that GNSS is not dependable. Reality here GNSS is still not dependable. This got me thinking is there some other clock source that is dependable. Then I remembered that our clocks historically were calibrated by sun and the sun and moon and stars... are all still there.

Raspberry pi compute module with like Aweigh module on poe Ethernet cable in a water proof box on roof is possible. This way if GNSS is jammed or spoofed for a long time atomic clock calibration can be done at-least once per day against the sun. This could removes the GNSS dependence reducing so making it optional extra. Dependence comes sun and atomic module.

See my problem here is the time board working around problem that can be avoided. Time of year and other things are also calculable from sun location in sky to earth position information this could also limit spoofing of GNSS information being able to check against local sun time/data.

I know the sun/moon data will have some error due to how land under our feet slowly moves.

I tried to update my TimeCard to FPGA release 10, but it is not showing on the bus after the update.

Hardware:

Time Card
Xilinx Platform Cable (Waveshare clone)

Software

Vivado Lab Edition 2022.1

Image

Factory_TimeCardProduction.bin release 10

Steps tested

• upgrade full flash to raw Factory_TimeCardProduction.bin
• Modified original dump and replace content starting @ 0x00400000 with theTimeCardProduction.bin
• Write bitstream directly to the FPGA RAM
• Update using devlink

Result

D14 is constantly lit, and the Time Card does not show on the bus.
trying to upgrade with devlink ends up with: ptp_ocp 0000:02:00.0: Can't find Flash SPI adapter

Does this release require some hardware reworks?
dmesg info about my HW:

[    4.516617] ptp_ocp 0000:02:00.0: enabling device (0100 -> 0102)
[    4.517114] ptp_ocp 0000:02:00.0: irq 16 out of range, skipping ts4
[    4.526202] ptp_ocp 0000:02:00.0: Version 1.2.0, clock PPS, device ptp0
[    4.526218] ptp_ocp 0000:02:00.0: Time: 1659174202.287690580, in-sync
[    4.526221] ptp_ocp 0000:02:00.0: version 8
[    4.526223] ptp_ocp 0000:02:00.0: regular image, version 8
[    4.526224] ptp_ocp 0000:02:00.0:  GNSS: /dev/ttyS5  @ 115200
[    4.526227] ptp_ocp 0000:02:00.0: GNSS2: /dev/ttyS6  @ 115200
[    4.526229] ptp_ocp 0000:02:00.0:   MAC: /dev/ttyS7  @  57600
[    4.526234] ptp_ocp 0000:02:00.0:  NMEA: /dev/ttyS8  @     -1
[ 2887.195004] ptp_ocp 0000:02:00.0: Can't find Flash SPI adapter

There is a reason why is this a hard limit or is it that lower has not been tried. If this card can work with generation 2.0/2.1 this opens a few other hardware options.

Raspberry Pi 4 Compute Module supporting boards can provide PCI 2.0 and RK3399 based boards can provide PCI 2.1.

Basically a 1U rack being able to hold primary secondary clock sync sources and few other extras.

For the Raspberry PI 4 Compute Module I am sure that "Jeff Geerling"
https://www.youtube.com/channel/UCR-DXc1voovS8nhAvccRZhg
would try the card.

Smaller setups its possible that something like a Raspberry PI 4 compute module would have enough processing power for like 50 machines worth of clock sync. Think shop point of sales system.

• What is "RV-3049-C3" (U10A and U10B, p.5,A3)?
• The labels on the off-page connectors on p. 6 seem to be interspersed with CR (0x0d) characters. The corresponding net names on other pages are OK.
• MP1482DS is marked "not recommended for new designs. refer to MP1476.
• There is no revision or date in the title block.
• U2 (p.4,A5) EEPROM I2C address is 0x00

I'm working on getting this thing working on a Raspberry Pi, running the latest version of Raspberry Pi OS:

$ uname -a
Linux cm4 5.10.52-v8+ #1441 SMP PREEMPT Tue Aug 3 18:14:03 BST 2021 aarch64 GNU/Linux

$ cat /etc/os-release
PRETTY_NAME="Debian GNU/Linux 10 (buster)"
NAME="Debian GNU/Linux"
VERSION_ID="10"
VERSION="10 (buster)"
VERSION_CODENAME=buster
ID=debian
HOME_URL="https://www.debian.org/"
SUPPORT_URL="https://www.debian.org/support"
BUG_REPORT_URL="https://bugs.debian.org/"

Right now the remake script fails with:

$ ./remake 
Could not locate kernel source for distribution 'debiangnu/linux'

But if I update the script to allow debian in addition to ubuntu:

diff --git a/Time-Card/DRV/remake b/Time-Card/DRV/remake
index 61e0c73..77ed189 100755
--- a/Time-Card/DRV/remake
+++ b/Time-Card/DRV/remake
@@ -10,7 +10,7 @@ if [ "$*" == "install" ]; then
 fi
 
 case "$DIST" in
-    ubuntu)
+    debian*|ubuntu)
         KDIR=/usr/src/linux-headers-${KVER}
         ;;
     centos*)

Then I get:

$ ./remake 
make: Entering directory '/usr/src/linux-headers-5.10.52-v8+'
  CC [M]  /home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.o
/home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.c:956:22: warning: ‘struct firmware’ declared inside parameter list will not be visible outside of this definition or declaration
         const struct firmware *fw)
                      ^~~~~~~~
/home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.c: In function ‘ptp_ocp_devlink_flash’:
/home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.c:968:12: error: dereferencing pointer to incomplete type ‘const struct firmware’
  resid = fw->size;
            ^~
/home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.c: In function ‘ptp_ocp_devlink_flash_update’:
/home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.c:1012:50: error: ‘struct devlink_flash_update_params’ has no member named ‘fw’
  err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
                                                  ^~
make[1]: *** [scripts/Makefile.build:280: /home/pi/Time-Appliance-Project/Time-Card/DRV/ptp_ocp.o] Error 1
make: *** [Makefile:1824: /home/pi/Time-Appliance-Project/Time-Card/DRV] Error 2
make: Leaving directory '/usr/src/linux-headers-5.10.52-v8+'

What is this external connector? It isn't in the schematic, but seems to be associated with the GNSS receiver.