Comments (3)
NetTimeLogic provides a Windows based software that allows you to monitor and set the configurations of the cores. This is an easier (since it is visual) alternative to directly changing values in Linux. In our recent driver though we have most of the settings accessible via the sysfs. This method can still be useful in case someone wants to use the time card without the PCIe being connected, such as event time stamper or IRIG-B generator.
from time-appliance-project.
Understood. Where does the "host PC running Windows" connect to the FPGA? I'm not seeing it on the AC7100 nor the Timing Card schematics.
from time-appliance-project.
In some versions of the timecard we have an UART (or USB-UART connection). However, the pins are always there in the FPGA design or on the SOM connector.
In the FPGA Design this are following pins:
#UART1
set_property PACKAGE_PIN P15 [get_ports Uart1TxDat_DatOut]
set_property PACKAGE_PIN P16 [get_ports Uart1RxDat_DatIn]
or on SOM Connector P1B:
B-71 UART_TXD
B-77 UART_RXD
Details about the UART Communication protocol as well as the Windows Tool you can find here:
https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/SOM/FPGA/UCM
from time-appliance-project.
Related Issues (20)
- Deprecated function use in 'ptp_ocp' driver HOT 5
- in CoreListFile.txt the high address of the AXI IIC CLOCK lines are wrong HOT 7
- Should the version numbers in the CoreList be the same as the version registers? HOT 3
- Connecting 1PPS and 10MHz outputs with 50 Ohm termination to another TimeCard 1PPS and 10MHz inputs
- Could not find device ttySX HOT 2
- OCXO Daughter Card V4 - Silkscreen Designator Mismatch for R8 and R33
- R6 Placement Interferes with Y3 (Abracon AOCJYR) on OCXO Daughter Card
- Fail in creating open source FPGA binaries from scratch HOT 5
- Open source FPGA build fails HOT 3
- LOF (ver 0.1) mechanical drawing is incomplete HOT 1
- SA45 osc daughtercard does not bring out LOCK signal HOT 1
- connector holes in Timecard I/O bracket aren't fully located HOT 1
- Production Timecard: bad termination on FPGA JTAG with USB HOT 2
- SMA TVS not connected to +3.3V HOT 1
- Production Timecard: mismatch between board and FPGA PCIe lane counts HOT 1
- experimental timecard v9 resistors R2 and R3 have the wrong values HOT 1
- Loading driver cause system crash on version of Beta-V1 HOT 12
- Time Card PCB queries from PCBway regarding vias in pad. HOT 2
- wrong UTC Offset to TAI during startup with NEO-M9N HOT 17
- Request to make TimeCardOS.bit available HOT 1
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from time-appliance-project.