Comments (1)
thschaub
commented on June 7, 2024
Hi @Satoshier
comments from the FPGA design perspective:
Q1: The UART and PCIe are internally in the FPGA image always parallel available (independent from the HW version you have). But to use the UART of course you need a HW version with the connector.
PCIe and UART have access via an AXI Interconnect to the same AXI Address space.
To use the UCM tool the time card has to be powered and of course the bitsream/binaries must be running.
Q2: To which binaries do you refer exactly?
There is a description in the Readme.pdf chapter 2 which might answer your question:
https://raw.githubusercontent.com/opencomputeproject/Time-Appliance-Project/master/Time-Card/SOM/FPGA/Readme.pdf
from time-appliance-project.
Related Issues (20)
- Deprecated function use in 'ptp_ocp' driver HOT 5
- in CoreListFile.txt the high address of the AXI IIC CLOCK lines are wrong HOT 7
- Should the version numbers in the CoreList be the same as the version registers? HOT 3
- Connecting 1PPS and 10MHz outputs with 50 Ohm termination to another TimeCard 1PPS and 10MHz inputs
- Could not find device ttySX HOT 2
- Prototype V7 schematic title block errors HOT 1
- locate SMB connector on RCB HOT 1
- Fail in creating open source FPGA binaries from scratch HOT 5
- Open source FPGA build fails HOT 3
- LOF (ver 0.1) mechanical drawing is incomplete HOT 1
- SA45 osc daughtercard does not bring out LOCK signal HOT 1
- connector holes in Timecard I/O bracket aren't fully located HOT 1
- Production Timecard: bad termination on FPGA JTAG with USB HOT 2
- SMA TVS not connected to +3.3V HOT 1
- Production Timecard: mismatch between board and FPGA PCIe lane counts HOT 1
- experimental timecard v9 resistors R2 and R3 have the wrong values HOT 1
- Loading driver cause system crash on version of Beta-V1 HOT 12
- Time Card PCB queries from PCBway regarding vias in pad. HOT 2
- wrong UTC Offset to TAI during startup with NEO-M9N HOT 17
- Request to make TimeCardOS.bit available HOT 1
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from time-appliance-project.