Comments (2)
This is a good catch. I corrected these issues in V8. I'll close this issue after uploading V8, please re-open if there are any other issues. Thank you!
from time-appliance-project.
Updated in V8 in Experimental HW folder, will close for now.
from time-appliance-project.
Related Issues (20)
- Deprecated function use in 'ptp_ocp' driver HOT 5
- in CoreListFile.txt the high address of the AXI IIC CLOCK lines are wrong HOT 7
- Should the version numbers in the CoreList be the same as the version registers? HOT 3
- Connecting 1PPS and 10MHz outputs with 50 Ohm termination to another TimeCard 1PPS and 10MHz inputs
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- Prototype V7 schematic title block errors HOT 1
- locate SMB connector on RCB HOT 1
- Fail in creating open source FPGA binaries from scratch HOT 5
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- LOF (ver 0.1) mechanical drawing is incomplete HOT 1
- SA45 osc daughtercard does not bring out LOCK signal HOT 1
- connector holes in Timecard I/O bracket aren't fully located HOT 1
- Production Timecard: bad termination on FPGA JTAG with USB HOT 2
- SMA TVS not connected to +3.3V HOT 1
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- Loading driver cause system crash on version of Beta-V1 HOT 12
- Time Card PCB queries from PCBway regarding vias in pad. HOT 2
- wrong UTC Offset to TAI during startup with NEO-M9N HOT 17
- Request to make TimeCardOS.bit available HOT 1
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from time-appliance-project.