UVM_INFO ./src/riscv_asm_program_gen.sv(275) @ 0: reporter [asm_gen] Randomizing call stack..done
instr_list = {instr_list[0:idx-1], new_instr, instr_list[idx:current_instr_cnt-1]};
|
xmsim: *W,RTSVQR (./src/riscv_instr_stream.sv,100|29): improper part-select index expression ordering for queues.

How can I specify weights for some instructions?
How can I add new custom sequences?

I saw you reference to test/riscv_instr_test_lib.sv but there is not test dir

How can I change the location of the program? I saw it starts from 0x0 now but want to change it to our ICCM(instruction closely coupled memory)? Do you have linkerscript or something similar?

Hi,

I am trying to figure out the reason for a GCC error that I am getting when I try to compile the assembly test output from riscv-dv.

Command executed:

riscv64-unknown-elf-gcc -march=rv64imc -mabi=lp64 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I/home/crevinn/riscv_dl/riscv-tools/riscv-tests/env/p -T/home/crevinn/riscv_dl/riscv-tools/riscv-tests/env/p/link.ld

GCC errors:

riscv_instr_crevinn_basic_1.0.S -o riscv_instr_crevinn_basic_1.0.S.o
riscv_instr_crevinn_basic_1.0.S: Assembler messages:
riscv_instr_crevinn_basic_1.0.S:113: Error: Improper CSRxI immediate (1678)
riscv_instr_crevinn_basic_1.0.S:124: Error: Improper CSRxI immediate (1692)
riscv_instr_crevinn_basic_1.0.S:133: Error: Improper CSRxI immediate (1096)
riscv_instr_crevinn_basic_1.0.S:137: Error: Improper CSRxI immediate (1296)
riscv_instr_crevinn_basic_1.0.S:185: Error: Improper CSRxI immediate (1956)
riscv_instr_crevinn_basic_1.0.S:201: Error: Improper CSRxI immediate (36)
riscv_instr_crevinn_basic_1.0.S:207: Error: Improper CSRxI immediate (495)
riscv_instr_crevinn_basic_1.0.S:210: Error: Improper CSRxI immediate (1549)
riscv_instr_crevinn_basic_1.0.S:232: Error: Improper CSRxI immediate (1096)
riscv_instr_crevinn_basic_1.0.S:274: Error: Improper CSRxI immediate (347)
riscv_instr_crevinn_basic_1.0.S:317: Error: Improper CSRxI immediate (57)

The following are the lines in the file "riscv_instr_crevinn_basic_1.0.S" which are contributing to the above errors.
csrrci s10, 0xcd1, 1678 // line 113
csrrci a5, 0xa86, 1692 // line 124
csrrsi t1, 0x80f, 1096 // line 133
csrrsi t6, 0xb91, 1296 // line 137
csrrsi s4, 0x3a6, 1956 // line 185
csrrsi a6, 0xdc6, 36 // line 201
csrrci a4, 0x379, 495 // line 207
csrrsi a7, 0x685, 1549 // line 210
csrrwi t3, 0xe89, 1096 // line 232
csrrsi a2, 0x6de, 347 // line 274
csrrsi s1, 0xdcc, 57 // line 317

The compiler seems to be stating any value above 32 is not allowed in for the csrrci, csrrsi, csrrwi opcodes.
When I look at page 22 of the riscv-spec-v2.2 this seems to state that the uimm value is 5 bits.

If I create a testcase with the csr generation turned off I can now get riscv-gcc to compile the assembly i.e.

cfg.no_csr_instr = 1'b1;

So I had a look at this and I was wondering why riscv_instr_base.sv the CSR* instructions are given the R and I FORMAT?

// CSR instructions
add_instr(CSRRW, R_FORMAT, CSR, RV32I, UIMM) add_instr(CSRRS, R_FORMAT, CSR, RV32I, UIMM)
add_instr(CSRRC, R_FORMAT, CSR, RV32I, UIMM) add_instr(CSRRWI, I_FORMAT, CSR, RV32I, UIMM)
add_instr(CSRRSI, I_FORMAT, CSR, RV32I, UIMM) add_instr(CSRRCI, I_FORMAT, CSR, RV32I, UIMM)

At the top of this file riscv_instr_base.sv the FORMAT is being used to constrain the imm_len.

// Immediate bit length for different instruction format
constraint imm_len_c {
solve imm_type before imm_len;
if(format inside {U_FORMAT, J_FORMAT}) {
imm_len == 20;
}
if(format inside {I_FORMAT, S_FORMAT, B_FORMAT}) {
imm_len == 11;
}

I changed this constraint to the following and I am no longer getting riscv-gcc compile errors from the generated tests.

constraint imm_len_c {
solve imm_type before imm_len;
solve format before imm_len; // POK

if(imm_type == UIMM) { // POK 
    imm_len == 5; // POK 
} else {    // POK
  if(format inside {U_FORMAT, J_FORMAT}) {
    imm_len == 20;
  }
  if(format inside {I_FORMAT, S_FORMAT, B_FORMAT}) {
    imm_len == 11;
  }

.....................................
....................................
} // POK

}

Some examples of the newly generated CSR commands inside riscv_instr_crevinn_basic_1.0.S are:

...................................................................
csrrwi a5, 0x74b, 12
csrrci a1, 0xeb9, 26
.....................................................................
csrrwi s0, 0x2ec, 10
.....................................................................
csrrsi s1, 0x492, 28
......................................................................
csrrci t5, 0x29c, 24
.......................................................................
csrrci s9, 0xdaa, 17
.......................................................................

should these not be RV64A for the instr_group?

// RV64A
add_instr(LR_D, R_FORMAT, LOAD, RV32A) add_instr(SC_D, R_FORMAT, STORE, RV32A)
add_instr(AMOSWAP_D, R_FORMAT, AMO, RV32A) add_instr(AMOADD_D, R_FORMAT, AMO, RV32A)
add_instr(AMOAND_D, R_FORMAT, AMO, RV32A) add_instr(AMOOR_D, R_FORMAT, AMO, RV32A)
add_instr(AMOXOR_D, R_FORMAT, AMO, RV32A) add_instr(AMOMIN_D, R_FORMAT, AMO, RV32A)
add_instr(AMOMAX_D, R_FORMAT, AMO, RV32A) add_instr(AMOMINU_D, R_FORMAT, AMO, RV32A)
`add_instr(AMOMAXU_D, R_FORMAT, AMO, RV32A)

are you going to support these?

In file riscv_page_table.sv,
function gen_page_table_section(.) always uses ".dword" for page table entries.
It will cause error when configuration is 32-bit mode.

If one core supports only imc ( -march=rv32imc), what is the best way to disable other ISA groups?

When I tried to use xrun for the simulator tool, I got the following:

$ ./run -test riscv_instr_base_test -tool xrun
unsupported simulator xrun
./run: line 106: return: can only `return' from a function or sourced script
Running test riscv_instr_base_test with xrun..
./run: line 136: riscv_instr_base_test: command not found
===========================================================
                Generated RISC-V assembly tests
 ----------------------------------------------------------

There is a check on line 105 of run that does not work correctly. It should have exit 1 instead of return.

Hi,

I noticed that following may not work in some conditions:

.data
.align 4;
instr_bin:
.data
.align 12
.word 0xfc410113, 0xc33314f5, 0x9b1703a1, 0x22230003, 0x8e890011, 0x34086a73, 0x00512423, 0x5a638f2d
.word 0xdf7300e6, 0x07b33405, 0x8e5140c2, 0x8e458579, 0x05339622, 0x91f341a6, 0x3cb33409, 0x25b30134
.word 0xefe700b4, 0xd163479a, 0xd0f3058e, 0x5eb33403, 0x9e6340fd, 0xa093019c, 0xe0731fb8, 0x1bbb3407
.word 0x28f303c2, 0x81633402, 0x99b303ec, 0x2a3301d4, 0x00b30133, 0x8b3340e0, 0x6c730142, 0x89e13402

I think the instr_bin label should be placed right before first ".word".
It works now only because the .data is placed with certain alignment ..

Also it would be nice to place this data to a separate section to allow move it anywhere by linker as it was done for data pages

File this bug to track the progress of A extension support. A few things to do:

• Create development branch for A extension support
• Add instruction enum in riscv_instr_pkg.sv
• Add A extension support in riscv_instr_base.sv
• Enable A extension in riscv_core_setting, pass gcc compilation
• Add dedicated instruction stream for A extension, similar to load store instructions
• Add dedicated test for A extension
• Merge development branch back to the master branch

Please feel free to add your feature request here. You are more than welcome if you want to take some tasks from the list.

update #92

I'm new with the riscv-dv and never dealt with python before.

I'm getting following error :

alexander.grobman/lx1/riscv-dv]% python3 run.py --test=riscv_arithmetic_basic_test
Tue, 03 Sep 2019 14:28:43 INFO Processing regression test list : /wdc/proj/riscv/mustang/users/alexander.grobman/lx1/riscv-dv/yaml/testlist.yaml, test: riscv_arithmetic_basic_test
Traceback (most recent call last):
File "/wdc/proj/riscv/mustang/users/alexander.grobman/lx1/riscv-dv/scripts/lib.py", line 38, in read_yaml
yaml_data = yaml.safe_load(f)
AttributeError: module 'yaml' has no attribute 'safe_load'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
File "run.py", line 433, in
main()
File "run.py", line 407, in main
process_regression_list(args.testlist, args.test, args.iterations, matched_list)
File "/wdc/proj/riscv/mustang/users/alexander.grobman/lx1/riscv-dv/scripts/lib.py", line 147, in process_regression_list
yaml_data = read_yaml(testlist)
File "/wdc/proj/riscv/mustang/users/alexander.grobman/lx1/riscv-dv/scripts/lib.py", line 39, in read_yaml
except yaml.YAMLError as exc:
AttributeError: module 'yaml' has no attribute 'YAMLError'

what's wrong?

We tried the current version of riscv-dv and found a lot of building error when running the command:
python3 run.py --test riscv_arithmetic_basic_test --simulator ius

The first line of the compile.log is:
function new(string name="");
ncvlog: *E,NEWOIC (./src/dv_defines.svh,19|15): The class constructor method 'new' is only allowed within a class declaration.
(`include file: ./src/dv_defines.svh line 19, file: ./src/riscv_instr_pkg.sv line 23)

Thanks for any advice!

After commit 23ad2e9 I am seeing an issue with the include_file macro during Xcelium (19.03.001) compile.

  `include_file(`RISCV_CORE_SETTING)
                                   |
xmvlog: *E,COFILX (./src/riscv_instr_pkg.sv,651|35): cannot open include file '``f``'.
(`define macro: include_file [./src/riscv_instr_pkg.sv line 25], file: ./src/riscv_instr_pkg.sv line 651)                                                                        

The syntax in this include_file macro does not seem to be LRM compliant. I believe it should be:

  `define include_file(f) `include `"f`"

Hi, I'm seeing errors when running ./run -test riscv_instr_base_test. I see the following 2 errors:

Error-[ICTA] Incompatible complex type
./src/riscv_instr_gen_config.sv, 31
  Incompatible complex type assignment
  Incompatible complex types cannot be used in assignments, initializations 
  and instantiations.
  
Error-[ICTA] Incompatible complex type
./src/riscv_loop_instr.sv, 156
  Incompatible complex type assignment
  Incompatible complex types cannot be used in assignments, initializations 
  and instantiations.  

Do you have any suggestions? I am using vcs 2016.6.

I set up the ibex example and I'm using the latest master of riscv-dv, and noticed that the comparison at the end doesn't work because the script "spike_log_to_trace_csv.py" does not produce any output in it's resulting csv file. Any clues on what might be going wrong?

With reference to changes in New YAML based regression flow #46, these are my observations:

1. README.md still uses -tool irun instead of ius for the new flow

2. Also suggest adding "run.py --help" as a first step to show the user all the new options and what the arguments may be since the README.md doesn't quite cover the newer options

3.--help says you expect SO and CO as arguments for -so and -co but that doesn't work for me so I ended up passing an int after looking at the code. Not passing an argument doesn't work either so the intent of the arguments to these options is not clear in the --help or README.md

4. --verbose VERBOSE doesn't work either so had to pass an int to get it going similar to 3 above

5. Does it expect RISCV_GCC to be set? Any other variables besides SPIKE_PATH? This should be mentioned in the README too

Need to verify branch predictor

Hi,
Regarding the log comparison could you please elaborate on how you verify rtl instruction trace ?
Thank you.

Hi,

why does the test create "binary" section then copies it to a reserved subroutine ?

why can't you just inject "illegals" as .long /.word/ .short between normal instructions like this?

add x1,x3,x5
.long 0xXXXXX
and t0,t2,t3

(I'm getting some problems with this type of test now - when another master (we have random DMA traffic to the internal data memory, which is storage for .data) overwrites the .data section of your binary with a random data, before it was copied to the code location.
Sometimes the data, overwriting your stuff appears to be legal branch/jump instruction to nowhere ...)

It will be very helpful if there will be a way to customize test generator sources such a way that pull requests won't effect these customizations. For ex riscv_core_setting.sv file is under the git control and if changed locally may cause pull problems.
Also any local updates to the source cause the same ...

we want to use our exception handlers init and exit code

I think it will greatly help to ease the test generator customization to user needs if standard pieces of the test template are included / Macroed and not generated by SV code.

These are exception /interrupt handlers, CPU init code , test exit code, etc.

the test template can be then as
.include "riscvdv_test_env.h"
INIT_CPU
generated test
EXIT
...

Hi, I try to run Questa simulator. I got the error: Error loading design.

./run -test riscv_instr_base_test -tool questa
Building RISC-V instruction generator...
Building RISC-V instruction generator...done
Running test riscv_instr_base_test to generate 1 tests
Error loading design
===========================================================
                Generated RISC-V assembly tests
 ----------------------------------------------------------

Could you help me resolve it? Thank you

seems that exception code goes to .data section:

.word 0x3a7db1e6, 0xd412cc8d, 0x735721c1, 0x881570db, 0x2f9b3971, 0x825922ad, 0xb5f05d35, 0xc1ae9a38
.align 4;
.align 5
_user_stack_start:
.rept 4999
.4byte 0x0
.endr
_user_stack_end:
.4byte 0x0
_kernel_start: .align 12
smode_program: slt t2, t0, t1
c.beqz a4, smode_program_stack_p
smode_program_stack_p:addi sp, sp, -52
sll s3, s2, s7
sw ra, 4(sp)
sw t0, 8(sp)
sw s9, 12(sp)
mulhsu s5, a2, ra
sw a2, 16(sp)
sw t3, 20(sp)
sw t1, 24(sp)
c.andi a3, 16

diag.exe: file format elf32-littleriscv

Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00011a38 00000000 00000000 00001000 21
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .text.init 000000da 00011a38 00011a38 00012a38 20
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .data 00039e22 00012000 00012000 00013000 212
CONTENTS, ALLOC, LOAD, DATA
3 .tohost 00000048 0004be40 0004be40 0004ce40 26
CONTENTS, ALLOC, LOAD, DATA

It should be nice to get things in correct sections to be able to move them around with linker:

.text, .data. .stack .init, .handlers

Also what is the mechanism to define multiple data sections and their addresses? ( we have several memory regions with different characteristics - internal data, instructions, I/O, external normal memories and I/O regions,)

We would like to have several text and data sections be placed in these "RTL/TB defined" addresses.

Hi, I am trying to use questasim with riscv-dv platform.
But during test generation, i get the following error.
Are there any documentation regarding the UVM errors ?

QuestaSim-64 vlog 10.5 Compiler 2016.02 Feb 12 2016
Start time: 12:16:06 on Aug 19,2019
vlog -64 -access=rwc -f ./files.f -sv -mfcu -cuname design_cuname "+define+UVM_REGEX_NO_DPI" -writetoplevels ./out_2019-08-19/top.list -l ./out_2019-08-19/compile.log 
-- Compiling package riscv_instr_pkg
-- Importing package mtiUvm.uvm_pkg (uvm-1.2 Built-in)
** Note: (vlog-2286) ./src/riscv_instr_pkg.sv(21): Using implicit +incdir+/sw/mentor/questa_10_5c/questasim/uvm-1.2/../verilog_src/uvm-1.2/src from import uvm_pkg
** Error: ** while parsing file included at ./src/riscv_instr_pkg.sv(774)
** at ./src/riscv_reg.sv(129): (vlog-2266) Expansion of macro 'DV_CHECK_FATAL' failed: The number of actual arguments (3) are not equal to the number of formal arguments (4).

trying to use:
Linux 32bit Questa Sim Version 10.7c_3 linux Dec 21 2018

python3 run.py --test riscv_rand_instr_test --simulator questa32 --iss spike,ovpsim --iterations 1 --seed 1234 --isa rv32i --mabi ilp32 --testlist yaml/testlist_work.yaml --iss_yaml yaml/iss_ovpsim.yaml
I get:
....

UVM_FATAL ./src/riscv_asm_program_gen.sv(1079) @ 0: reporter [asm_gen] Check failed (new_instr_stream.randomize()) Randomization failed!

if I edit yaml/testlist_work.yaml and remove one of the lines:
+directed_instr_*
it does not matter which one, then the generator creates a legal .S file and all works.

thanks
Simon

Hi,

I'm getting some jump/subs test are running too long CPU gets to a sub call and seems never gets out. Are you sure that these sequences always finish?

this is one

from git SHA 6069ea3
run.int xrun -R -svseed 1854640120 +UVM_TESTNAME=riscv_instr_base_test +num_of_tests=1 +asm_file_name=test +instr_cnt=2000 +bare_program_mode=1 +num_of_sub_program=20 +directed_instr_0=riscv_load_store_rand_instr_stream,8

git diff setting/riscv_core_setting.sv

// XLEN
-parameter int XLEN = 64;
+//AG: parameter int XLEN = 64;
+parameter int XLEN = 32;

// Parameter for SATP mode, set to BARE if address translation is not supported
-parameter satp_mode_t SATP_MODE = SV39;
+//AG: parameter satp_mode_t SATP_MODE = SV39;
+parameter satp_mode_t SATP_MODE = BARE;

// Supported Privileged mode
-privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE};
+//AG: privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE};
+privileged_mode_t supported_privileged_mode[] = { MACHINE_MODE};

// Unsupported instructions
riscv_instr_name_t unsupported_instr[];

// ISA supported by the processor
-riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C, RV32A, RV64A};
+//AG: riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M, RV32C, RV64C, RV32A, RV64A};
+riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32A};

// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
@@ -42,7 +46,9 @@ bit support_debug_mode = 0;
bit support_umode_trap = 0;

// Support sfence.vma instruction
-bit support_sfence = 1;
+//AG: bit support_sfence = 1;
+bit support_sfence = 0;
+
No S/U CSRs

Hi,
Right now I am trying to generate tests with a subset of supported instruction group namely "rv64im". I would appreciate it if you could point out where I am wrong.
1)Following the README.md and manipulating
riscv_core_settings.sv:

  ...
  riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV64I, RV64M};
  //supported but not used = {RV32C, RV64C}
  ...

2)After, these commands are run

  ./run -tool vcs -test all
  ./iss_sim -iss spike -isa rv64im -abi lp64

3)The problem is here.
"iss_sim" outputs assembler errors regarding "C" extention.
"""

iss start
iss_processed_command_line
gcc compile start

riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S:6295: Error: unrecognized opcode `c.beqz a0,sub_3_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_sfence_exception_test.1.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S
./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S:10742: Error: unrecognized opcode `c.bnez a1,sub_2_stack_p'
./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S:13064: Error: unrecognized opcode `c.bnez a2,sub_3_stack_p'
./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S:26722: Error: unrecognized opcode `c.bnez a1,smode_ls_umem_program_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_no_fence_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_no_fence_test.1.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S:487: Error: unrecognized opcode `c.beqz s1,j__main_sub_1_1'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S:711: Error: unrecognized opcode `c.bnez s1,sub_4_stack_p'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S:7948: Error: unrecognized opcode `c.beqz a4,j_sub_1_sub_2_3'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S:18635: Error: unrecognized opcode `c.bnez a2,j_sub_3_sub_4_8'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S:19171: Error: unrecognized opcode `c.beqz a2,sub_5_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_rand_instr_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_jump_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_rand_jump_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_rand_jump_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_ebreak_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_ebreak_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_ebreak_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S
./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S:4593: Error: unrecognized opcode `c.bnez s0,sub_3_stack_p'
./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S:8499: Error: unrecognized opcode `c.beqz a0,sub_5_stack_p'
./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S:8695: Error: unrecognized opcode `c.bnez a4,sub_1_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_page_table_exception_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_no_fence_test.0.S
./out_2019-08-15/asm_tests/riscv_no_fence_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_no_fence_test.0.S:18550: Error: unrecognized opcode `c.beqz a3,j_sub_2_sub_5_6'
Convert ./out_2019-08-15/asm_tests/riscv_no_fence_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_no_fence_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_no_fence_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S:551: Error: unrecognized opcode `c.beqz s1,j__main_sub_1_3'
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S:1324: Error: unrecognized opcode `c.beqz a5,j_sub_3_sub_5_5'
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S:1686: Error: unrecognized opcode `c.beqz s0,j_sub_3_sub_4_6'
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S:2897: Error: unrecognized opcode `c.bnez a1,sub_5_stack_p'
./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S:20295: Error: unrecognized opcode `c.beqz a0,j_sub_2_sub_3_4'
Convert ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_sfence_exception_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S
./out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S:17269: Error: unrecognized opcode `c.beqz a4,j_sub_7_sub_11_11'
Convert ./out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_rand_jump_test.1.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_page_table_exception_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_wfi_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_wfi_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_wfi_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_machine_mode_rand_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.1.S
Convert ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.1.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_ebreak_test.0.S
./out_2019-08-15/asm_tests/riscv_ebreak_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_ebreak_test.0.S:244: Error: unrecognized opcode `c.bnez a0,j__main_sub_1_1'
Convert ./out_2019-08-15/asm_tests/riscv_ebreak_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_ebreak_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_ebreak_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S
./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S:2377: Error: unrecognized opcode `c.beqz a2,j__main_sub_1_1'
./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S:15874: Error: unrecognized opcode `c.bnez s0,j_sub_4_sub_5_7'
Convert ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_illegal_instr_test.1.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_mmu_stress_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S
./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:181: Error: unrecognized opcode `c.beqz s1,j__main_sub_1_1'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:25608: Error: unrecognized opcode `c.bnez a0,smode_accessible_umode_program_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_wfi_test.0.S
./out_2019-08-15/asm_tests/riscv_wfi_test.0.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_wfi_test.0.S:16425: Error: unrecognized opcode `c.beqz a3,sub_4_stack_p'
./out_2019-08-15/asm_tests/riscv_wfi_test.0.S:26711: Error: unrecognized opcode `c.bnez a1,smode_ls_umem_program_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_wfi_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_wfi_test.0.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_wfi_test.0.S.o': No such file
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_hint_instr_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_hint_instr_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_hint_instr_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_arithmetic_basic_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.0.S
Convert ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.0.S.o to ./out_2019-08-15/asm_tests/riscv_privileged_mode_rand_test.0.S.bin
riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S
./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S: Assembler messages:
./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S:2020: Error: unrecognized opcode `c.bnez a5,j__main_sub_1_1'
./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S:16470: Error: unrecognized opcode `c.bnez a0,sub_2_stack_p'
./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S:26894: Error: unrecognized opcode `c.bnez a4,smode_ls_umem_program_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_hint_instr_test.1.S.o': No such file
gcc compile end
Running spike: riscv_sfence_exception_test.1.S.o
Running spike: riscv_no_fence_test.1.S.o
Running spike: riscv_mmu_stress_test.1.S.o
Running spike: riscv_rand_instr_test.0.S.o
Running spike: riscv_rand_jump_test.0.S.o
Running spike: riscv_ebreak_test.1.S.o
Running spike: riscv_page_table_exception_test.0.S.o
Running spike: riscv_no_fence_test.0.S.o
Running spike: riscv_sfence_exception_test.0.S.o
Running spike: riscv_arithmetic_basic_test.1.S.o
Running spike: riscv_rand_jump_test.1.S.o
Running spike: riscv_machine_mode_rand_test.0.S.o
Running spike: riscv_page_table_exception_test.1.S.o
Running spike: riscv_wfi_test.1.S.o
Running spike: riscv_machine_mode_rand_test.1.S.o
Running spike: riscv_privileged_mode_rand_test.1.S.o
Running spike: riscv_ebreak_test.0.S.o
Running spike: riscv_illegal_instr_test.0.S.o
Running spike: riscv_illegal_instr_test.1.S.o
Running spike: riscv_mmu_stress_test.0.S.o
Running spike: riscv_rand_instr_test.1.S.o
Running spike: riscv_wfi_test.0.S.o
Running spike: riscv_hint_instr_test.0.S.o
Running spike: riscv_arithmetic_basic_test.0.S.o
Running spike: riscv_privileged_mode_rand_test.0.S.o
Running spike: riscv_hint_instr_test.1.S.o

"""

The current regression flow is a mix of bash and python script, which is really meant to be used as a simple flow for initial bring up. As more and more ISS and RTL simulator are added to the flow, it becomes pretty hard to extend and maintain. On the other hand, there's a need of a better end to end flow to control how the program is generated, how to simulate the program, and how the result should be compared.

To resolve these issues, we are implementing a new end-to-end flow based on YAML configuration files. The purpose is make this flow more configurable and extendable. I have submitted the initial prototype of the flow: 18cca8b

List of YAML configure files:

• Test list
• ISS configuration
• RTL simulator configuration
• Privileged CSR specification

Here's a few commands you can try:

// Run full regression with VCS
python3 run.py --simulator=vcs
// Run full regression with VCS
python3 run.py --test=riscv_arithmetic_basic_test --iterations=10 
// For complete command reference
python3 run.py --help

I will be adding a few more features to this flow. Feel free to give your feedback and suggestion here.

It doesn't compile now:
unique {loop_regs, default_reserved_regs};
|
xmvlog: *E,MSTBER (./src/riscv_instr_gen_config.sv,263|43): Expecting a random variable (declared with the 'rand' modifier).
unique {loop_regs, ZERO, scratch_reg, default_reserved_regs};
|
xmvlog: *E,MSTBER (./src/riscv_instr_gen_config.sv,267|26): Expecting a random variable (declared with the 'rand' modifier).
unique {loop_regs, ZERO, scratch_reg, default_reserved_regs};
|
xmvlog: *E,MSTBER (./src/riscv_instr_gen_config.sv,267|62): Expecting a random variable (declared with the 'rand' modifier).
unique {loop_regs, ZERO, scratch_reg, default_reserved_regs,
|
xmvlog: *E,MSTBER (./src/riscv_instr_gen_config.sv,272|28): Expecting a random variable (declared with the 'rand' modifier).
unique {loop_regs, ZERO, scratch_reg, default_reserved_regs,
|
xmvlog: E,MSTBER (./src/riscv_instr_gen_config.sv,272|64): Expecting a random variable (declared with the 'rand' modifier).
import riscv_instr_pkg::;
|
xmvlog: *E,NOPBIND (./test/riscv_instr_test_pkg.sv,20|23): Package riscv_instr_pkg could not be bound.
(include file: ./test/riscv_instr_base_test.sv line 18, file: ./test/riscv_instr_test_pkg.sv line 23) riscv_instr_gen_config cfg; | xmvlog: *E,NOIPRT (./test/riscv_instr_base_test.sv,20|23): Unrecognized declaration 'riscv_instr_gen_config' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog]. (include file: ./test/riscv_instr_base_test.sv line 20, file: ./test/riscv_instr_test_pkg.sv line 23)
riscv_asm_program_gen asm_gen;
|
xmvlog: E,NOIPRT (./test/riscv_instr_base_test.sv,23|22): Unrecognized declaration 'riscv_asm_program_gen' could be an unsupported keyword, a spelling mistake or missing instance port list '()' [SystemVerilog].
(`include file: ./test/riscv_instr_base_test.sv line 23, file: ./test/riscv_instr_test_pkg.sv line 23)
import riscv_instr_test_pkg::;
|
xmvlog: *E,NOPBIND (./test/riscv_instr_gen_tb_top.sv,22|28): Package riscv_instr_test_pkg could not be bound.
xrun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
~

it looks like the test generation is quite slow ( at least with Cadence xrun )- it seems we simulate the tests much faster than they are generated. Are there any plans to run verilog profiler to improve generation speed?

It took ~19min to generate 20 riscv_rand_jump_test tests..

Riscv-dv supported instruction set IMAC now, Will it support float and double instruction? Or this program has been working on it? the mainstream risc-v core supported RV64GC instruction set. So I think it's urgent. May I cooperate with you?

Seeing following NOA fail in my runs with VCS version 2014.10:

UVM_INFO @ 0: reporter [RNTST] Running test riscv_instr_base_test...
UVM_INFO riscv_instr_gen_config.sv(311) @ 0: reporter [cfg] supported_privileged_mode = 3
UVM_INFO riscv_instr_gen_config.sv(311) @ 0: reporter [cfg] supported_privileged_mode = 3
UVM_INFO riscv_instr_base_test.sv(107) @ 0: uvm_test_top [uvm_test_top] riscv_instr_gen_config is randomized:
-------------------------------------------------------------
Name                      Type                    Size  Value
-------------------------------------------------------------
cfg                       riscv_instr_gen_config  -     @364 
  main_program_instr_cnt  integral                32    'h4  
  sub_program_instr_cnt   sa(integral)            5     -    
    [0]                   integral                32    'h58 
    [1]                   integral                32    'h4  
    [2]                   integral                32    'h1b 
    [3]                   integral                32    'h16 
    [4]                   integral                32    'h37 
-------------------------------------------------------------

UVM_INFO riscv_instr_base_test.sv(99) @ 0: uvm_test_top [uvm_test_top] All directed instruction is applied
UVM_INFO riscv_asm_program_gen.sv(602) @ 0: reporter [asm_gen] Randomizing page tables, totally 7 page tables, mode = USER_MODE
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 0, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 1, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 2, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 3, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 4, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 5, num of PTE: 512
UVM_INFO riscv_page_table_list.sv(123) @ 0: reporter [page_table_list] Randomizing page table 6, num of PTE: 512
UVM_INFO riscv_asm_program_gen.sv(607) @ 0: reporter [asm_gen] Finished creating page tables
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_0_PTE_0, v = 1, level = 2
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_0_PTE_1, v = 1, level = 2
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_1_PTE_0, v = 1, level = 1
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_1_PTE_1, v = 1, level = 1
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_2_PTE_0, v = 1, level = 1
UVM_INFO riscv_page_table_list.sv(443) @ 0: reporter [page_table_list] Processing PT_2_PTE_1, v = 1, level = 1
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@sub_1 [sub_1] Start generating 88 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@sub_1 [sub_1] Finishing instruction generation
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@sub_2 [sub_2] Start generating 4 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@sub_2 [sub_2] Finishing instruction generation
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@sub_3 [sub_3] Start generating 27 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@sub_3 [sub_3] Finishing instruction generation
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@sub_4 [sub_4] Start generating 22 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@sub_4 [sub_4] Finishing instruction generation
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@sub_5 [sub_5] Start generating 55 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@sub_5 [sub_5] Finishing instruction generation
UVM_INFO riscv_instr_sequence.sv(72) @ 0: reporter@@main_program [main_program] Start generating 4 instruction
UVM_INFO riscv_instr_sequence.sv(81) @ 0: reporter@@main_program [main_program] Finishing instruction generation
UVM_INFO riscv_asm_program_gen.sv(106) @ 0: reporter [asm_gen] Randomizing call stack

Error-[NOA] Null object access
riscv_instr_sequence.sv, 136
  The object at dereference depth 2 is being used before it was 
  constructed/allocated.
  Please make sure that the object is allocated before using it. 
  
  #0 in \riscv_instr_sequence::post_process_instr  at 
  riscv_instr_sequence.sv:136
  #1 in \riscv_asm_program_gen::gen_program  at riscv_asm_program_gen.sv:127
  #2 in \riscv_instr_base_test::run_phase  at riscv_instr_base_test.sv:100
  #3 in \uvm_run_phase::exec_task  at 
  /apps/vcsmx/etc/uvm-1.2/base/uvm_common_phases.svh:269
  #4 in \uvm_task_phase::execute  at 
  /apps/vcsmx/etc/uvm-1.2/base/uvm_task_phase.svh:152
  #5 in \uvm_phase::execute_phase  at 
  /apps/vcsmx/etc/uvm-1.2/base/uvm_phase.svh:1408
  #6 in \uvm_phase::m_run_phases  at 
  /apps/vcsmx/etc/uvm-1.2/base/uvm_phase.svh:2213
  #7 in \uvm_root::run_test  at /apps/vcsmx/etc/uvm-1.2/base/uvm_root.svh:513
  #8 in run_test at /apps/vcsmx/etc/uvm-1.2/base/uvm_globals.svh:43

Hi,
I have a question regarding ISA extension group G (IMFAD).
Will there be support for remainder ?
If not what is the suggested practice for adding support for them ?
Thank you,

I'm having a problem with this script. Last working version was git SHA 80d4294. It seems that the first 'sed' command deletes the entire log file, and after that there are no instructions to convert. I see this also happening with the latest https://github.com/lowRISC/ibex, at git SHA 1e8381b. Every comparison fails because the log files from Spike are empty after this script runs on them.

I did the following change

// ISA supported by the processor
riscv_instr_group_t supported_isa[] = {RV32I, RV32M, RV32C};

But then got these errors
run.int ./run -tool irun
Your DISPLAY variable is set to :3.0
Your job has been submitted to NC - Interactive Queue
Fairshare= /class/gui
Resources= guiHost CORES/0 Limit:gui_riscv_@USER@
Env = SNAPPROP(@jobid@)+D(DISPLAY=uls-ep-vhpcetx09:3.0)
Command = vw ./run -tool irun
Logfile = /dev/null
JobURL = http://uls-ep-vhpcnc02:8271/cgi/node.cgi?id=001652034
JobId = 001652034
<<<>>>
instr_name == SD; rs2 == saved_regs[i]; rs1 == SP; imm == 8 * (i+1);)
|
ncvlog: *E,UNDIDN (./src/riscv_directed_instr_lib.sv,216|78): 'SD': undeclared identifier [12.5(IEEE)].
instr_name == LD; rd == saved_regs[i]; rs1 == SP; imm == 8 * (i+1);)
|
ncvlog: *E,UNDIDN (./src/riscv_directed_instr_lib.sv,282|77): 'LD': undeclared identifier [12.5(IEEE)].
allowed_instr = {LW, SW, LWU, allowed_instr};
|
ncvlog: *E,UNDIDN (./src/riscv_load_store_instr_lib.sv,110|35): 'LWU': undeclared identifier [12.5(IEEE)].
allowed_instr = {LD, SD, allowed_instr};
|
ncvlog: *E,UNDIDN (./src/riscv_load_store_instr_lib.sv,116|26): 'LD': undeclared identifier [12.5(IEEE)].
allowed_instr = {LD, SD, allowed_instr};
|
ncvlog: *E,UNDIDN (./src/riscv_load_store_instr_lib.sv,116|30): 'SD': undeclared identifier [12.5(IEEE)].
allowed_instr = {C_LD, C_SD, allowed_instr};
|
ncvlog: *E,UNDIDN (./src/riscv_load_store_instr_lib.sv,118|30): 'C_LD': undeclared identifier [12.5(IEEE)].

the name in the run.py to select different yaml files tends to be the file start with _yaml, eg
iss_yaml, csr_yaml, simulator_yaml
and then it is --testlist
pls make it consistent
suggest --testlist_yaml
thanks

Hi,

I tried running page fault exception tests out of the box on a RISC-V implementation. I see that the generated test did not initialize any PMP registers. Since page tables are to be accessed with S mode privilege, the implementation throws an access fault.

The same program works differently on Spike ISA simulator and throws PAGE FAULT because it initializes a set of PMP registers at reset to grant read-write-execute access to the entire memory region. See here

Spike may also not be compliant, but I believe this is a known issue.

     instr_group[instr.group].push_back(instr_name);
                            |

xmvlog: *W,ENUMERR (riscv-dv/src/riscv_instr_gen_config.sv,503|32): This assignment is a violation of SystemVerilog strong typing rules for

strange if I generate a test with 100 instructions our script doesn't compile it -linker fails. For 1000 instructions it links.

the failure looks like:

(.text+0x544): relocation truncated to fit: R_RISCV_PCREL_LO12_S against `.L0 '
vascom: ERROR > linker/loader failed (ret=256)

objdump from test.o

...
00000544 <write_tohost>:
544: 00000f17 auipc t5,0x0
548: 003f2023 sw gp,0(t5) # 544 <write_tohost>

0000054c <_exit>:
54c: bfe5 j 544 <write_tohost>

I'm generating test as:

xrun -R -svseed 699553742 +UVM_TESTNAME=riscv_instr_base_test +num_of_tests=1 +asm_file_name=test +instr_cnt=100 +bare_program_mode=1 +num_of_sub_program=5 +directed_instr_0=riscv_lr_sc_instr_stream,10 +directed_instr_1=riscv_amo_instr_stream,10

Do you have any plans to add coverage to the generator to collect various instructions properties, generated. For ex, types, branch offsets, L/S offsets , reg operands etc?

I am trying to install riscv-gcc tool chain by following below commands
1.git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
2.sudo yum install autoconf automake libmpc-devel mpfr-devel gmp-devel gawk bison flex texinfo patchutils gcc gcc-c++ zlib-devel expat-devel
3../configure --prefix=/opt/riscv
4. make linux

While following these above steps and after running step 4.i am getting compilation error
cc1: internal compiler error: Aborted.
Can you please tell correct steps for installing riscv-gcc toolchain
Can you also please tell after above toolchain installatiom. what should be the value of env variable RISCV_GCC.

Regards
Munish

Hi,

Since we implemented B instructions I need to make sure that these are not generated as illegals or at least do not target SP or other reserved registers. How do I enforce this?

              srai       t2, s4, 23
              .4byte 0x21aed133 # kIllegalFunc7
              slt        s0, a1, a7
              fence

80003ea4: 417a5393 srai t2,s4,0x17
80003ea8: 21aed133 0x21aed133
80003eac: 0115a433 slt s0,a1,a7

UVM_INFO [tracer] @816500.0ns: => x7 = ffffff00
UVM_INFO [tracer] @816500.0ns: => @816500 #3075 C0 80003ea4 [417a5393] srai x7, x20, 0x17 OK
UVM_INFO [tracer] @816600.0ns: => x2 = fffffc00
UVM_INFO [tracer] @816600.0ns: => @816600 #3076 C0 80003ea8 [21aed133] sro x2, x29, x26 OK
UVM_INFO [tracer] @816700.0ns: => x8 = 00000001
UVM_INFO [tracer] @816700.0ns: => @816700 #3077 C0 80003eac [0115a433] slt x8, x11, x17 OK

this illegal corrupts stack pointer (x2)...

When I run

python3 run.py --test riscv_arithmetic_basic_test --iss spike --verbose --isa rv64g

I see the following line at the terminal:

/bin/sh: line 1: +disable_comparessed_instr=1: command not found

When I grep the repository I couldn't find a file which includes disable_comparessed_instr word (except run.py).

There is no disable_compressed_instr word in the repository either.

For reference:
https://github.com/google/riscv-dv/blob/2370dc84cf14d46715466960d55ddd93ab830874/run.py#L222

First of all thanks for the nice code!
I am trying to use your code to setup and run big simulation on Emulator. If succeed I will share my results to community.
I am really new in RISC open-core, please help guys to get good DUT-RTL for your code.
Looking here: https://riscv.org/risc-v-cores/, but so many cores do not know which one to choose.

would you please provide some help with DUT selection? Preferable FPGA confirmed.
Also I checked the TB is self-checking right?

Is there way to generate tests in any other directory than riscv-dv?

We usually don't run in repository. We run randoms in separate working area which is cleaned periodically.

the generator file list contains "./' references, pointing to the current directory ...