Subset of Instruction Groups & riscv_core_settings.sv about riscv-dv HOT 6 CLOSED

Do you want to disable compressed instruction in one test or all tests?

from riscv-dv.

I tried to disable for all the tests. But if there is a test-specific solution I can use it as well.

from riscv-dv.

Please try run riscv_non_compressed_instr_test test
https://github.com/google/riscv-dv/blob/master/yaml/testlist.yaml#L83

If the processor doesn't support compressed instruction, you can disable it in the processor setting
https://github.com/google/riscv-dv/blob/master/setting/riscv_core_setting.sv#L33

from riscv-dv.

For the first link, I will try the riscv_non_compressed_instr_test.
For the second link, that's what I've tried to do. But at the riscv_gcc compilation step, there were still compressed instructions from the instruction stream resulting in assembler error. My question is this an expected behavior.

./iss_sim -iss spike -isa rv64im -abi lp64

riscv_gcc compiling : ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S
./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S: Assembler messages:  ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:181: Error: unrecognized opcode `c.beqz s1,j__main_sub_1_1'
./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S:25608: Error: unrecognized opcode `c.bnez a0,smode_accessible_umode_program_stack_p'
Convert ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o to ./out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.bin
/home/riscv-toolchain/riscv-gnu-ins/bin/riscv64-unknown-elf-objcopy: './out_2019-08-15/asm_tests/riscv_rand_instr_test.1.S.o': No such file

from riscv-dv.

This issue should be fixed by #81 , can you try again?

from riscv-dv.

I am closing this issue for now, please let me know if it doesn't work for you.

from riscv-dv.