curliph Goto Github PK

16fusb

The 16FUSB is a software implementation of the USB low-speed for PIC16F628/628A microcontroller.

2dconv-fpga

A 2D convolution hardware implementation written in Verilog

adc-lvds

Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS

adv_dbg_if

Universal Advanced JTAG Debug Interface

adv_jtag_bridge

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

ahb3lite_interconnect

AHB3-Lite Interconnect

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals for embedded AI applications and smart sensors.

akaros

Akaros Operating System

align-public

anycore-riscv-src

The RTL source for AnyCore RISC-V

aor3000

The aoR3000 is a MIPS R3000A compatible core capable of booting the Linux kernel version 3.16 in about 3 seconds and with a rating of 48.74 BogoMIPS. It features a compatible MMU, but no FPU.

apicula

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

archlinux-cross-bootstrap

ariane

Ariane is a 6-stage RISC-V CPU

ariscv

Verilog implementation of a RISC-V core

art

🎨 ASCII art library for Python

arty-s7-multinic

ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface

atomicc

Generate Verilog from Atomicc IR files (which are generated from llvm-translate)

avalonedit

The WPF-based text editor component used in SharpDevelop

avatar-gdbstub

GDB stub that allows debugging of embedded devices

avr-tcc

Tiny C Compiler for AVR architecture

avr_debug

Source level debugger for Arduino - GDB stub for Atmega328 microcontroller used in Arduino Uno.

avrdudess

A GUI for AVRDUDE

avsdbgp_3v3_sky130_v2

awesome-blockchains

A collection about awesome blockchains - open distributed public databases w/ crypto hashes incl. git ;-). Blockchains are the new tulips :tulip::tulip::tulip:. Distributed is the new centralized.

awesome-hdl

Hardware Description Languages

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

bch_verilog

Verilog based BCH encoder/decoder