saggit01 Goto Github PK

8x8-internet-switch

Adding verilog code

ardu_serie

Arduino is the Apollo Project of the maker movement!!!

arduinocore-avr

The Official Arduino AVR core

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

avr

Some AVR code that I wrote for my ATmega32 based board. Code is in Assembly and C.

avra

Assembler for the Atmel AVR microcontroller family

basic-chat

Bluetooth Low Energy App for iOS using Swift.

bipartite-graph-checker

Find disjoint vertex sets of bipartite graphs

blackjack

A BlackJack game for iOS using Swift

cache-simulator

A cache simulator implemented in C for my computer systems class. The simulator takes a Valgrind trace file as input as well as parameters for the cache and accurately outputs the expected number of hits, misses, and evictions for the trace file. This project was based off the Cache Lab from CMU.

cache-simulator-1

A simulated cache memory in C

cachelab

CacheLab Project for CS2011. Team members: Chad Underhill and Sam Coache

class-projects

code_snippets

coding-interview-university

A complete computer science study plan to become a software engineer.

coursera-bioinformatics

My solution to Bioinformatics Specialization (Finding Hidden Messages in DNA; Genome Sequencing; Comparing Genes, Proteins, and Genomes; Molecular Evolution; Genomic Data Science and Clustering; Finding Mutations in DNA and Proteins; Bioinformatics Capstone: Big Data in Biology)

cpp-lru-cache

Simple and reliable LRU cache for c++ based on hashmap and linkedlist

cpppatterns-patterns

A repository of modern C++ patterns curated by the community.

cs50

CS50 related materials and PSETs

cs50-1

All of my projects for Harvard's CS50 2018

cs50-final-project

cs50 final project

cs576-fall-2019

BMI/CS 576 (Fall 2019): Introduction To Bioinformatics @ UWMadison

csapp-labs

《Computer Systems A Programmer's Perspective Second Edition》 important Labs

django-ecommerce

An e-commerce website built with Django

dlx

Structural RTL Implementation of a 32-bit MIPS-like Microprocessor with Branch Prediction Unit and Forwarding Logic

dlx--mips-processor-core

Implementation of the DLX RISC processor from RTL down to physical design

dualcoreprocessor

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

fleetapp

how-to-secure-anything

How to systematically secure anything: a repository about security engineering

interview

Everything you need to prepare for your technical interview