Comments (8)
scottj97
commented on May 7, 2024
For boolean options like these, python's argparse offers action='store_true' (instead of type=int).
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taoliug
commented on May 7, 2024
Thanks for reporting, I will take a look and get back to you.
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danghai
commented on May 7, 2024
I got the same issue relating to RISCV_GCC:
danghai@ubuntu:~/google/riscv-dv$ python3 run.py --test=riscv_page_table_exception_test --iss=spike
Processing regression test list : /home/danghai/google/riscv-dv/yaml/testlist.yaml, test: riscv_page_table_exception_test
Found matched tests: riscv_page_table_exception_test, iterations:2
Processing simulator setup file : /home/danghai/google/riscv-dv/yaml/simulator.yaml
Found matching simulator: vcs
Building RISC-V instruction generator
Running RISC-V instruction generator
Generating 2 riscv_page_table_exception_test
Please set the environment variable RISCV_GCC
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taoliug
commented on May 7, 2024
Just submitted PR #56 to address the issues, please let me know if there's anything else not working for you.
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taoliug
commented on May 7, 2024
I haven't tested with questa though, please let me know if you have issue running with questa.
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danghai
commented on May 7, 2024
Hi @taoliug , I create a PR to make it work for questa.
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vandanaprabhu
commented on May 7, 2024
The questa flow appears to be broken (hence the empty asm file) because of the spaces preceding the multiline vlog and opt options simulator.yaml file.
When I changed these to tabs as shown below and the compile and sim worked
Also the correct command is sv_seed <seed> (not svsejd <seed> )value is not being passed correctly it appears.
- tool: questa
compile_cmd:
- "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
- "vlog -64
-access=rwc
-f <cwd>/files.f
-sv
-mfcu -cuname design_cuname
+define+UVM_REGEX_NO_DPI
-writetoplevels <out>/top.list
-l <out>/compile.log <cmp_opts>"
- "vopt -64 -debug
+designfile -f <out>/top.list
-o design_opt"
sim_cmd: >
vsim -64 -c -do <cwd>/questa_sim.tcl design_opt <sim_opts> -sv_seed <seed>
Let me know if you want me to create a pull request but I believe this should fix Hai’s issue.
Vandana
… On Aug 1, 2019, at 3:55 PM, taoliug ***@***.***> wrote:
I haven't tested with questa though, please let me know if you have issue running with questa.
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taoliug
commented on May 7, 2024
Please feel free to create a PR if it fixes the questa sim issue on your side. Thanks.
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Related Issues (20)
- Definition of Functional Coverage
- VCS2018：Incompatible complex type HOT 3
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- [page table] There is a error in page table !
- kIllegalCompressedOpcode generates valid instruction (```c.fswsp```) when XLEN=32 HOT 1
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