ucb-bar / riscv-sodor Goto Github PK

educational microarchitectures for risc-v isa

License: Other

Makefile 1.76% Python 16.92% Scala 79.55% M4 0.09% Verilog 0.52% Assembly 1.15% C 0.02%

riscv-sodor's Introduction

About The Sodor Processor Collection

Note: This repo has been updated to be used with the Chipyard SoC Generator. For the old self-contained version of Sodor (which is no longer maintained), see https://github.com/ucb-bar/riscv-sodor/tree/sodor-old.

Diagrams: Sodor Github wiki

More documentation: Librecores Sodor wiki

Downstream development: Librecores Sodor

This repo has been put together to demonstrate a number of simple RISC-V integer pipelines written in Chisel:

1-stage (essentially an ISA simulator)
2-stage (demonstrates pipelining in Chisel)
3-stage (uses sequential memory; supports both Harvard and Princeton versions)
5-stage (can toggle between fully bypassed or fully interlocked)
"bus"-based micro-coded implementation

All of the cores implement the RISC-V 32b integer base user-level ISA (RV32I) version 2.0. None of the cores support virtual memory, and thus only implement the Machine-level (M-mode) of the Privileged ISA v1.10 .

All processors talk to a simple scratchpad memory (asynchronous, single-cycle), with no backing outer memory (the 3-stage is the exception - its scratchpad is synchronous). Programs are loaded in via JTAG or TSI, scratchpads 3-port memories (instruction, data, debug).

This repository is set up to use the Verilog file generated by Chisel3 which is fed to Verilator along with a test harness in C++ to generate and run the Sodor emulators.

This repo works great as an undergraduate lab (and has been used by Berkeley's CS152 class for 3 semesters and counting). See doc/ for an example, as well as for some processor diagrams. Be careful though - admittedly some of those documents may become dated as things like the Privileged ISA evolve.

Getting the repo and Building the processor emulators

This repo is NOT a self-running repository. Please follow the instruction in https://chipyard.readthedocs.io/en/latest/ to set up Chipyard and simulate Sodor cores.

FAQ

What is the goal of these cores?

First and foremost, to provide a set of easy to understand cores that users can easily modify and play with. Sodor is useful both as a quick introduction to the RISC-V ISA and to the hardware construction language Chisel3.

Are there any diagrams of these cores?

Diagrams of some of the processors can be found either in the Sodor Github wiki, in doc/, or in doc/lab1.pdf. A more comprehensive write-up on the micro-code implementation can be found at the CS152 website.

How do I generate Verilog code for use on a FPGA?

Chisel3 outputs verilog by default which can be generated by

cd emulator/rv32_1stage
make generated-src/Top.v

I want to help! Where do I go?

You can participate in the Sodor conversation on gitter. Downstream development is also taking place at Librecores. Major milestones will be pulled back here. Check it out! We also accept pull requests here!

TODO

Here is an informal list of things that would be nice to get done. Feel free to contribute!

Reduce the port count on the scratchpad memory by having the HTIF port share one of the cpu ports.
Provide a Verilog test harness, and put the 3-stage on a FPGA.
Add support for the ma_addr, ma_fetch ISA tests. This requires detecting misaligned address exceptions.
Greatly cleanup the common/csr.scala file, to make it clearer and more understandable.
Refactor the stall, kill, fencei, and exception logic of the 5-stage to be more understandable.
Update the u-code to properly handle illegal instructions (rv32mi-p-illegal) and to properly handle exceptions generated by the CSR file (rv32mi-p-csr).

riscv-sodor's People

Contributors

Stargazers

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Forkers

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riscv-sodor's Issues

Build error verilator

Hy there,

I completed the git clone and RISC-V front-end install to /usr/local/
After

./configure --with-riscv=/usr/local
make

I get

g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=0 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -O1 -std=c++11  -g -I/home/e6430/risc-v/riscv-sodor/emulator/common -I/usr/local/include -I/home/e6430/risc-v/riscv-sodor/riscv-fesvr/fesvr  -L/usr/local/lib -Wl,-rpath,/usr/local/lib -L. -lpthread -DVERILATOR -include /home/e6430/risc-v/riscv-sodor/emulator/common/verilator.h   -c -o emulator.o /home/e6430/risc-v/riscv-sodor/emulator/common/emulator.cpp
In file included from <command-line>:
/home/e6430/risc-v/riscv-sodor/emulator/common/verilator.h:15:19: error: ‘string’ does not name a type; did you mean ‘stdin’?
   bool open(const string& name) override {
                   ^~~~~~
                   stdin
/home/e6430/risc-v/riscv-sodor/emulator/common/verilator.h:15:8: error: ‘bool VerilatedVcdFILE::open(const int&)’ marked ‘override’, but does not override
   bool open(const string& name) override {
        ^~~~
make[2]: *** [VTop.mk:63: emulator.o] Error 1
make[2]: Leaving directory '/home/e6430/risc-v/riscv-sodor/emulator/rv32_1stage/obj_dir'
make[1]: *** [/home/e6430/risc-v/riscv-sodor/emulator/common/Makefile.include:104: emulator] Error 2
make[1]: Leaving directory '/home/e6430/risc-v/riscv-sodor/emulator/rv32_1stage'
make: *** [Makefile:108: emulator/rv32_1stage/emulator] Error 2

My setup:
Kubuntu 18.10

verilator --version
Verilator 3.922 2018-03-17 rev UNKNOWN_REV

Has anybody seen this error before?
Might be the Verilator version?

setup error

Hi, when I try to build the sodor emulator, there are some errors. How can I solve it?

[info] [0.001] Elaborating design...

Sodor Tile: creating Asynchronous Scratchpad Memory of size 2048 kB

[info] [0.425] Done elaborating.
[error] (run-main) firrtl.passes.PassExceptions:
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.versionhi <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.reserved0 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sbaccess128 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.reserved3 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] : io.debugmem.req.bits.typ <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 203:50:@270.6] : node _GEN_24 = mux(_T_238, sbaddr, VOID) @[debug.scala 203:50:@270.6]
[error] @[debug.scala 169:54:@149.4] : node _GEN_49 = mux(_T_302, _GEN_24, VOID) @[debug.scala 169:54:@149.4]
[error] @[debug.scala 240:137:@322.4] : node _GEN_65 = mux(_T_390, sbaddr, _GEN_49) @[debug.scala 240:137:@322.4]
[error] : io.debugmem.req.bits.addr <= _GEN_65
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 222:24:@298.6] : node _GEN_57 = mux(command.write, UInt<1>("h1"), VOID) @[debug.scala 222:24:@298.6]
[error] @[debug.scala 221:54:@297.4] : node _GEN_60 = mux(_T_373, _GEN_57, VOID) @[debug.scala 221:54:@297.4]
[error] : io.ddpath.validreq <= _GEN_60
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sbsingleread <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.allrunning <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.allresumeack <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.allunavail <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.anynonexistent <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.anyhalted <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.reserved2 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.anyrunning <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 203:50:@270.6] : node _GEN_25 = mux(_T_238, sbdata, VOID) @[debug.scala 203:50:@270.6]
[error] @[debug.scala 169:54:@149.4] : node _GEN_50 = mux(_T_302, _GEN_25, VOID) @[debug.scala 169:54:@149.4]
[error] : io.debugmem.req.bits.data <= _GEN_50
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sbautoread <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 203:50:@270.6] : node _GEN_27 = mux(_T_238, io.dmi.req.valid, VOID) @[debug.scala 203:50:@270.6]
[error] @[debug.scala 169:54:@149.4] : node _GEN_52 = mux(_T_302, _GEN_27, VOID) @[debug.scala 169:54:@149.4]
[error] @[debug.scala 240:137:@322.4] : node _GEN_67 = mux(_T_390, io.dmi.req.valid, _GEN_52) @[debug.scala 240:137:@322.4]
[error] : io.debugmem.req.valid <= _GEN_67
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sberror <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 203:50:@270.6] : node _GEN_26 = mux(_T_238, UInt<1>("h1"), VOID) @[debug.scala 203:50:@270.6]
[error] @[debug.scala 169:54:@149.4] : node _GEN_51 = mux(_T_302, _GEN_26, VOID) @[debug.scala 169:54:@149.4]
[error] @[debug.scala 231:98:@310.4] : node _GEN_63 = mux(_T_380, UInt<1>("h0"), _GEN_51) @[debug.scala 231:98:@310.4]
[error] @[debug.scala 240:137:@322.4] : node _GEN_66 = mux(_T_390, UInt<1>("h0"), _GEN_63) @[debug.scala 240:137:@322.4]
[error] : io.debugmem.req.bits.fcn <= _GEN_66
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.reserved1 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.cfgstrvalid <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.anyunavail <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] @[debug.scala 222:24:@298.6] : node _GEN_56 = mux(command.write, data0, VOID) @[debug.scala 222:24:@298.6]
[error] @[debug.scala 221:54:@297.4] : node _GEN_59 = mux(_T_373, _GEN_56, VOID) @[debug.scala 221:54:@297.4]
[error] : io.ddpath.wdata <= _GEN_59
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.allnonexistent <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sbaccess64 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.cmderr <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.reserved1 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.reserved0 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
[error] : io.ddpath.resetpc <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.authbusy <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.allhalted <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.anyresumeack <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
[error] : abstractcsReset.busy <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
[error] : sbcsreset.sbautoincrement <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
[error] : dmstatusReset.reserved0 <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
[error] : io.dmem.req.bits.addr <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
[error] : io.imem.req.bits.addr <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
[error] : io.dmem.req.bits.data <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
[error] : io.imem.req.bits.data <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@1074.4] : [module CSRFile] Reference io is not fully initialized.
[error] : io.singleStep <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@1074.4] : [module CSRFile] Reference io is not fully initialized.
[error] @[csr.scala 284:23:@1897.4] : node _GEN_3 = mux(io.exception, UInt<32>("h80000004"), VOID) @[csr.scala 284:23:@1897.4]
[error] @[csr.scala 297:38:@1917.4] : node _GEN_8 = mux(_T_974, reg_dpc, _GEN_3) @[csr.scala 297:38:@1917.4]
[error] @[csr.scala 304:41:@1925.4] : node _GEN_12 = mux(_T_979, reg_mepc, _GEN_8) @[csr.scala 304:41:@1925.4]
[error] @[csr.scala 312:18:@1931.4] : node _GEN_13 = mux(insn_call, UInt<32>("h80000004"), _GEN_12) @[csr.scala 312:18:@1931.4]
[error] @[csr.scala 318:19:@1937.4] : node _GEN_15 = mux(insn_break, UInt<32>("h80000004"), _GEN_13) @[csr.scala 318:19:@1937.4]
[error] : io.evec <= _GEN_15
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.dmem.req.bits.typ <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.dmem.req.valid <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.dmem.req.bits.fcn <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.imem.req.bits.fcn <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.imem.req.bits.typ <= VOID
[error] firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
[error] : io.imem.req.bits.data <= VOID
[error] firrtl.passes.PassException: 48 errors detected!
firrtl.passes.PassExceptions:
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.versionhi <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.reserved0 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sbaccess128 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.reserved3 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
: io.debugmem.req.bits.typ <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 203:50:@270.6] : node _GEN_24 = mux(_T_238, sbaddr, VOID) @[debug.scala 203:50:@270.6]
@[debug.scala 169:54:@149.4] : node _GEN_49 = mux(_T_302, _GEN_24, VOID) @[debug.scala 169:54:@149.4]
@[debug.scala 240:137:@322.4] : node _GEN_65 = mux(_T_390, sbaddr, _GEN_49) @[debug.scala 240:137:@322.4]
: io.debugmem.req.bits.addr <= _GEN_65
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 222:24:@298.6] : node _GEN_57 = mux(command.write, UInt<1>("h1"), VOID) @[debug.scala 222:24:@298.6]
@[debug.scala 221:54:@297.4] : node _GEN_60 = mux(_T_373, _GEN_57, VOID) @[debug.scala 221:54:@297.4]
: io.ddpath.validreq <= _GEN_60
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sbsingleread <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.allrunning <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.allresumeack <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.allunavail <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.anynonexistent <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.anyhalted <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.reserved2 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.anyrunning <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 203:50:@270.6] : node _GEN_25 = mux(_T_238, sbdata, VOID) @[debug.scala 203:50:@270.6]
@[debug.scala 169:54:@149.4] : node _GEN_50 = mux(_T_302, _GEN_25, VOID) @[debug.scala 169:54:@149.4]
: io.debugmem.req.bits.data <= _GEN_50
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sbautoread <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 203:50:@270.6] : node _GEN_27 = mux(_T_238, io.dmi.req.valid, VOID) @[debug.scala 203:50:@270.6]
@[debug.scala 169:54:@149.4] : node _GEN_52 = mux(_T_302, _GEN_27, VOID) @[debug.scala 169:54:@149.4]
@[debug.scala 240:137:@322.4] : node _GEN_67 = mux(_T_390, io.dmi.req.valid, _GEN_52) @[debug.scala 240:137:@322.4]
: io.debugmem.req.valid <= _GEN_67
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sberror <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 203:50:@270.6] : node _GEN_26 = mux(_T_238, UInt<1>("h1"), VOID) @[debug.scala 203:50:@270.6]
@[debug.scala 169:54:@149.4] : node _GEN_51 = mux(_T_302, _GEN_26, VOID) @[debug.scala 169:54:@149.4]
@[debug.scala 231:98:@310.4] : node _GEN_63 = mux(_T_380, UInt<1>("h0"), _GEN_51) @[debug.scala 231:98:@310.4]
@[debug.scala 240:137:@322.4] : node _GEN_66 = mux(_T_390, UInt<1>("h0"), _GEN_63) @[debug.scala 240:137:@322.4]
: io.debugmem.req.bits.fcn <= _GEN_66
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.reserved1 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.cfgstrvalid <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.anyunavail <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
@[debug.scala 222:24:@298.6] : node _GEN_56 = mux(command.write, data0, VOID) @[debug.scala 222:24:@298.6]
@[debug.scala 221:54:@297.4] : node _GEN_59 = mux(_T_373, _GEN_56, VOID) @[debug.scala 221:54:@297.4]
: io.ddpath.wdata <= _GEN_59
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.allnonexistent <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sbaccess64 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.cmderr <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.reserved1 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.reserved0 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@6.4] : [module DebugModule] Reference io is not fully initialized.
: io.ddpath.resetpc <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.authbusy <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.allhalted <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.anyresumeack <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 128:29:@21.4] : [module DebugModule] Reference abstractcsReset is not fully initialized.
: abstractcsReset.busy <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 121:23:@14.4] : [module DebugModule] Reference sbcsreset is not fully initialized.
: sbcsreset.sbautoincrement <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[debug.scala 117:28:@10.4] : [module DebugModule] Reference dmstatusReset is not fully initialized.
: dmstatusReset.reserved0 <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
: io.dmem.req.bits.addr <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
: io.imem.req.bits.addr <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
: io.dmem.req.bits.data <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@356.4] : [module CtlPath] Reference io is not fully initialized.
: io.imem.req.bits.data <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@1074.4] : [module CSRFile] Reference io is not fully initialized.
: io.singleStep <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@1074.4] : [module CSRFile] Reference io is not fully initialized.
@[csr.scala 284:23:@1897.4] : node _GEN_3 = mux(io.exception, UInt<32>("h80000004"), VOID) @[csr.scala 284:23:@1897.4]
@[csr.scala 297:38:@1917.4] : node _GEN_8 = mux(_T_974, reg_dpc, _GEN_3) @[csr.scala 297:38:@1917.4]
@[csr.scala 304:41:@1925.4] : node _GEN_12 = mux(_T_979, reg_mepc, _GEN_8) @[csr.scala 304:41:@1925.4]
@[csr.scala 312:18:@1931.4] : node _GEN_13 = mux(insn_call, UInt<32>("h80000004"), _GEN_12) @[csr.scala 312:18:@1931.4]
@[csr.scala 318:19:@1937.4] : node _GEN_15 = mux(insn_break, UInt<32>("h80000004"), _GEN_13) @[csr.scala 318:19:@1937.4]
: io.evec <= _GEN_15
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.dmem.req.bits.typ <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.dmem.req.valid <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.dmem.req.bits.fcn <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.imem.req.bits.fcn <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.imem.req.bits.typ <= VOID
firrtl.passes.CheckInitialization$RefNotInitializedException: @[:@2698.4] : [module DatPath] Reference io is not fully initialized.
: io.imem.req.bits.data <= VOID
firrtl.passes.PassException: 48 errors detected!
at firrtl.passes.Errors.trigger(Passes.scala:45)
at firrtl.passes.CheckInitialization$.run(CheckInitialization.scala:92)
at firrtl.passes.Pass$class.execute(Passes.scala:24)
at firrtl.passes.CheckInitialization$.execute(CheckInitialization.scala:17)
at firrtl.Transform$$anonfun$4.apply(Compiler.scala:201)
at firrtl.Transform$$anonfun$4.apply(Compiler.scala:201)
at firrtl.Utils$.time(Utils.scala:135)
at firrtl.Transform.runTransform(Compiler.scala:201)
at firrtl.SeqTransformBased$$anonfun$runTransforms$1.apply(Compiler.scala:253)
at firrtl.SeqTransformBased$$anonfun$runTransforms$1.apply(Compiler.scala:253)
at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
at scala.collection.immutable.List.foldLeft(List.scala:84)
at firrtl.SeqTransformBased$class.runTransforms(Compiler.scala:253)
at firrtl.SeqTransform.runTransforms(Compiler.scala:257)
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:1628)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:1628)
at scala.Option.foreach(Option.scala:236)
at sbt.BuildCommon$class.toError(Defaults.scala:1628)
at sbt.Defaults$.toError(Defaults.scala:34)
at sbt.Defaults$$anonfun$runTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:647)
at sbt.Defaults$$anonfun$runTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:645)
at scala.Function1$$anonfun$compose$1.apply(Function1.scala:47)
at sbt.$tilde$greater$$anonfun$$u2219$1.apply(TypeFunctions.scala:42)
at sbt.std.Transform$$anon$4.work(System.scala:64)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:237)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:237)
at sbt.ErrorHandling$.wideConvert(ErrorHandling.scala:18)
[error] (rv32_1stage/compile:run) Nonzero exit code: 1
[error] Total time: 38 s, completed Dec 8, 2017 10:33:23 PM
/home/zhpzhp/riscv-sodor/emulator/common/Makefile.include:80: recipe for target 'generated-src/Top.v' failed
make[1]: *** [generated-src/Top.v] Error 1
make[1]: Leaving directory '/home/zhpzhp/riscv-sodor/emulator/rv32_1stage'
Makefile:108: recipe for target 'emulator/rv32_1stage/emulator' failed
make: *** [emulator/rv32_1stage/emulator] Error 2

bit patterns of shift immediate instructions

In the file riscv-sodor/src/common/instructions.scala, I noticed that the bit patterns of the shift immediate instructions slli, srli and srai only have 6 bits on the left while the specification has 7.
Is this an error?

Why is it necessary to use RISCV_LINK_OPTS for compilation?

I changed the branch to cs152-sp18.

I followed the compile template to compile my code. There are some errors about undefined reference function, even though I include the lib.

I found the problem was -nostdlib option in RISCV_LINK_OPTS in Makefile for benchmark. If I omitted it, there was following error.

riscv64-unknown-elf-gcc: error: riscv64-unknown-elf-gcc: No such file or directory.

I want to know the reason of using these options and are there any ways to compile it to get report without using these options?

error when compile riscv-sodor/riscv-tests/benchmarks with XLEN=32

Could someone help me?

riscv32-unknown-elf-gcc -I./../env -I./common -I./qsort -I./rsort -I./towers -I./vvadd -I./multiply -I./mm -I./dhrystone -I./spmv -I./mt-vvadd -I./mt-matmul -I./pmp -I./median -DPREALLOCATE=1 -mcmodel=medany -static -std=gnu99 -O2 -ffast-math -fno-common -fno-builtin-printf -static -nostdlib -nostartfiles -lgcc -T ./common/test.ld -o qsort.riscv ./qsort/qsort_main.c ./common/syscalls.c ./common/crt.S
/home/lustre/riscv_bin/lib/gcc/riscv32-unknown-elf/8.3.0/../../../../riscv32-unknown-elf/bin/ld: /tmp/ccU07r7t.o: in function `.L48':
syscalls.c:(.text+0x158): undefined reference to `__umoddi3'
/home/lustre/riscv_bin/lib/gcc/riscv32-unknown-elf/8.3.0/../../../../riscv32-unknown-elf/bin/ld: /tmp/ccU07r7t.o: in function `.L59':
syscalls.c:(.text+0x188): undefined reference to `__udivdi3'
/home/lustre/riscv_bin/lib/gcc/riscv32-unknown-elf/8.3.0/../../../../riscv32-unknown-elf/bin/ld: syscalls.c:(.text+0x1a0): undefined reference to `__umoddi3'
collect2: error: ld returned 1 exit status
Makefile:54: recipe for target 'qsort.riscv' failed
make: *** [qsort.riscv] Error 1

make run-emulator error

I am using g++-4.9.2 in ubuntu 12.04, and encounter the following Error 120 when try make run-emulator. There are no more hint on what the problems are? Any one can help?

./emulator +max-cycles=30000 +verbose +coremap-random +loadmem=output/simple.hex none 2> output/simple.out
make[1]: [output/simple.out] Error 120 (ignored)
./emulator +max-cycles=30000 +verbose +coremap-random +loadmem=output/add.hex none 2> output/add.out
make[1]: [output/add.out] Error 120 (ignored)
./emulator +max-cycles=30000 +verbose +coremap-random +loadmem=output/addi.hex none 2> output/addi.out
make[1]: [output/addi.out] Error 120 (ignored)
....

make run emulator error

the make process is finished, and make run-emulator error shown as follow：

hessen@ParaComp:~/risc-v/riscv-sodor$ make run-emulator

running basedir/Makefile: make run-emulator

make -C emulator/rv32_1stage/ run
make[1]: Entering directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage'
make -C /home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/fesvr libfesvr.a
make[2]: Entering directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/fesvr'
make[2]: 'libfesvr.a' is up to date.
make[2]: Leaving directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/fesvr'
verilator --cc --exe  --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/hessen/risc-v/riscv-sodor/vsrc -O3 -CFLAGS "-O1 -std=c++11 -g -I/home/hessen/risc-v/riscv-sodor/emulator/common -I/home/hessen/risc-v/riscv-sodor/riscv-isa-sim -DVERILATOR -include /home/hessen/risc-v/riscv-sodor/emulator/common/verilator.h" -LDFLAGS " /home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/fesvr/libfesvr.a -lpthread" -o /home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/emulator generated-src/Top.v /home/hessen/risc-v/riscv-sodor/vsrc/SimDTM.v /home/hessen/risc-v/riscv-sodor/emulator/common/emulator.cpp /home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/SimDTM.o
make -C /home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/obj_dir -f VTop.mk
make[2]: Entering directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/obj_dir'
make[2]: Nothing to be done for 'default'.
make[2]: Leaving directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage/obj_dir'
./emulator +max-cycles=30000 /home/hessen/risc-v/riscv-sodor/install/riscv-tests/rv32ui-p-simple 3>&1 1>&2 2>&3 | /home/hessen/risc-v/riscv-sodor/emulator/common/tracer.py > output/rv32ui-p-simple.out
/home/hessen/risc-v/riscv-sodor/emulator/common/Makefile.include:225: recipe for target 'output/rv32ui-p-simple.out' failed
make[1]: *** [output/rv32ui-p-simple.out] Error 255
make[1]: Leaving directory '/home/hessen/risc-v/riscv-sodor/emulator/rv32_1stage'
Makefile:99: recipe for target 'emulator/rv32_1stage/generated-src/timestamp' failed
make: *** [emulator/rv32_1stage/generated-src/timestamp] Error 2

in output/rv32ui-p-simple.out this file, show a error

*** FAILED *** (timeout) after 30000 cycles

No emulator directory??

Hi...
My question cab be a really silly one but there is no emulator directory anymore in this repo.... So how can I make those rv32 cores that you have in src/main/scala directory?

"make reports" for benchmarks failing

When I run make reports after 'make run-emulator' I get errors like these grep CPI emulator/rv32_1stage/output/.out
make: [rv32_1stage-report-cpi] Error 1 (ignored)
and test-results.xml is all 0
$ make reports
emulator/rv32_1stage/output/dhrystone.riscv.out emulator/rv32_1stage/output/median.riscv.out emulator/rv32_1stage/output/multiply.riscv.out emulator/rv32_1stage/output/qsort.riscv.out emulator/rv32_1stage/output/rv32mi-p-csr.out emulator/rv32_1stage/output/rv32mi-p-illegal.out emulator/rv32_1stage/output/rv32mi-p-sbreak.out emulator/rv32_1stage/output/rv32mi-p-scall.out emulator/rv32_1stage/output/rv32ui-p-addi.out emulator/rv32_1stage/output/rv32ui-p-add.out emulator/rv32_1stage/output/rv32ui-p-andi.out emulator/rv32_1stage/output/rv32ui-p-and.out emulator/rv32_1stage/output/rv32ui-p-auipc.out emulator/rv32_1stage/output/rv32ui-p-beq.out emulator/rv32_1stage/output/rv32ui-p-bge.out emulator/rv32_1stage/output/rv32ui-p-bgeu.out emulator/rv32_1stage/output/rv32ui-p-blt.out emulator/rv32_1stage/output/rv32ui-p-bltu.out emulator/rv32_1stage/output/rv32ui-p-bne.out emulator/rv32_1stage/output/rv32ui-p-fence_i.out emulator/rv32_1stage/output/rv32ui-p-jal.out emulator/rv32_1stage/output/rv32ui-p-jalr.out emulator/rv32_1stage/output/rv32ui-p-j.out emulator/rv32_1stage/output/rv32ui-p-lb.out emulator/rv32_1stage/output/rv32ui-p-lbu.out emulator/rv32_1stage/output/rv32ui-p-lh.out emulator/rv32_1stage/output/rv32ui-p-lhu.out emulator/rv32_1stage/output/rv32ui-p-lui.out emulator/rv32_1stage/output/rv32ui-p-lw.out emulator/rv32_1stage/output/rv32ui-p-ori.out emulator/rv32_1stage/output/rv32ui-p-or.out emulator/rv32_1stage/output/rv32ui-p-sb.out emulator/rv32_1stage/output/rv32ui-p-sh.out emulator/rv32_1stage/output/rv32ui-p-simple.out emulator/rv32_1stage/output/rv32ui-p-slli.out emulator/rv32_1stage/output/rv32ui-p-sll.out emulator/rv32_1stage/output/rv32ui-p-slti.out emulator/rv32_1stage/output/rv32ui-p-slt.out emulator/rv32_1stage/output/rv32ui-p-srai.out emulator/rv32_1stage/output/rv32ui-p-sra.out emulator/rv32_1stage/output/rv32ui-p-sub.out emulator/rv32_1stage/output/rv32ui-p-sw.out emulator/rv32_1stage/output/rv32ui-p-xori.out emulator/rv32_1stage/output/rv32ui-p-xor.out emulator/rv32_1stage/output/towers.riscv.out emulator/rv32_1stage/output/vvadd.riscv.out emulator/rv32_2stage/output/dhrystone.riscv.out emulator/rv32_2stage/output/median.riscv.out emulator/rv32_2stage/output/multiply.riscv.out emulator/rv32_2stage/output/qsort.riscv.out emulator/rv32_2stage/output/rv32mi-p-csr.out emulator/rv32_2stage/output/rv32mi-p-illegal.out emulator/rv32_2stage/output/rv32mi-p-sbreak.out emulator/rv32_2stage/output/rv32mi-p-scall.out emulator/rv32_2stage/output/rv32ui-p-addi.out emulator/rv32_2stage/output/rv32ui-p-add.out emulator/rv32_2stage/output/rv32ui-p-andi.out emulator/rv32_2stage/output/rv32ui-p-and.out emulator/rv32_2stage/output/rv32ui-p-auipc.out emulator/rv32_2stage/output/rv32ui-p-beq.out emulator/rv32_2stage/output/rv32ui-p-bge.out emulator/rv32_2stage/output/rv32ui-p-bgeu.out emulator/rv32_2stage/output/rv32ui-p-blt.out emulator/rv32_2stage/output/rv32ui-p-bltu.out emulator/rv32_2stage/output/rv32ui-p-bne.out emulator/rv32_2stage/output/rv32ui-p-fence_i.out emulator/rv32_2stage/output/rv32ui-p-jal.out emulator/rv32_2stage/output/rv32ui-p-jalr.out emulator/rv32_2stage/output/rv32ui-p-j.out emulator/rv32_2stage/output/rv32ui-p-lb.out emulator/rv32_2stage/output/rv32ui-p-lbu.out emulator/rv32_2stage/output/rv32ui-p-lh.out emulator/rv32_2stage/output/rv32ui-p-lhu.out emulator/rv32_2stage/output/rv32ui-p-lui.out emulator/rv32_2stage/output/rv32ui-p-lw.out emulator/rv32_2stage/output/rv32ui-p-ori.out emulator/rv32_2stage/output/rv32ui-p-or.out emulator/rv32_2stage/output/rv32ui-p-sb.out emulator/rv32_2stage/output/rv32ui-p-sh.out emulator/rv32_2stage/output/rv32ui-p-simple.out emulator/rv32_2stage/output/rv32ui-p-slli.out emulator/rv32_2stage/output/rv32ui-p-sll.out emulator/rv32_2stage/output/rv32ui-p-slti.out emulator/rv32_2stage/output/rv32ui-p-slt.out emulator/rv32_2stage/output/rv32ui-p-srai.out emulator/rv32_2stage/output/rv32ui-p-sra.out emulator/rv32_2stage/output/rv32ui-p-sub.out emulator/rv32_2stage/output/rv32ui-p-sw.out emulator/rv32_2stage/output/rv32ui-p-xori.out emulator/rv32_2stage/output/rv32ui-p-xor.out emulator/rv32_2stage/output/towers.riscv.out emulator/rv32_2stage/output/vvadd.riscv.out emulator/rv32_3stage/output/dhrystone.riscv.out emulator/rv32_3stage/output/median.riscv.out emulator/rv32_3stage/output/multiply.riscv.out emulator/rv32_3stage/output/qsort.riscv.out emulator/rv32_3stage/output/rv32mi-p-csr.out emulator/rv32_3stage/output/rv32mi-p-illegal.out emulator/rv32_3stage/output/rv32mi-p-sbreak.out emulator/rv32_3stage/output/rv32mi-p-scall.out emulator/rv32_3stage/output/rv32ui-p-addi.out emulator/rv32_3stage/output/rv32ui-p-add.out emulator/rv32_3stage/output/rv32ui-p-andi.out emulator/rv32_3stage/output/rv32ui-p-and.out emulator/rv32_3stage/output/rv32ui-p-auipc.out emulator/rv32_3stage/output/rv32ui-p-beq.out emulator/rv32_3stage/output/rv32ui-p-bge.out emulator/rv32_3stage/output/rv32ui-p-bgeu.out emulator/rv32_3stage/output/rv32ui-p-blt.out emulator/rv32_3stage/output/rv32ui-p-bltu.out emulator/rv32_3stage/output/rv32ui-p-bne.out emulator/rv32_3stage/output/rv32ui-p-fence_i.out emulator/rv32_3stage/output/rv32ui-p-jal.out emulator/rv32_3stage/output/rv32ui-p-jalr.out emulator/rv32_3stage/output/rv32ui-p-j.out emulator/rv32_3stage/output/rv32ui-p-lb.out emulator/rv32_3stage/output/rv32ui-p-lbu.out emulator/rv32_3stage/output/rv32ui-p-lh.out emulator/rv32_3stage/output/rv32ui-p-lhu.out emulator/rv32_3stage/output/rv32ui-p-lui.out emulator/rv32_3stage/output/rv32ui-p-lw.out emulator/rv32_3stage/output/rv32ui-p-ori.out emulator/rv32_3stage/output/rv32ui-p-or.out emulator/rv32_3stage/output/rv32ui-p-sb.out emulator/rv32_3stage/output/rv32ui-p-sh.out emulator/rv32_3stage/output/rv32ui-p-simple.out emulator/rv32_3stage/output/rv32ui-p-slli.out emulator/rv32_3stage/output/rv32ui-p-sll.out emulator/rv32_3stage/output/rv32ui-p-slti.out emulator/rv32_3stage/output/rv32ui-p-slt.out emulator/rv32_3stage/output/rv32ui-p-srai.out emulator/rv32_3stage/output/rv32ui-p-sra.out emulator/rv32_3stage/output/rv32ui-p-sub.out emulator/rv32_3stage/output/rv32ui-p-sw.out emulator/rv32_3stage/output/rv32ui-p-xori.out emulator/rv32_3stage/output/rv32ui-p-xor.out emulator/rv32_3stage/output/towers.riscv.out emulator/rv32_3stage/output/vvadd.riscv.out emulator/rv32_5stage/output/dhrystone.riscv.out emulator/rv32_5stage/output/median.riscv.out emulator/rv32_5stage/output/multiply.riscv.out emulator/rv32_5stage/output/qsort.riscv.out emulator/rv32_5stage/output/rv32mi-p-csr.out emulator/rv32_5stage/output/rv32mi-p-illegal.out emulator/rv32_5stage/output/rv32mi-p-sbreak.out emulator/rv32_5stage/output/rv32mi-p-scall.out emulator/rv32_5stage/output/rv32ui-p-addi.out emulator/rv32_5stage/output/rv32ui-p-add.out emulator/rv32_5stage/output/rv32ui-p-andi.out emulator/rv32_5stage/output/rv32ui-p-and.out emulator/rv32_5stage/output/rv32ui-p-auipc.out emulator/rv32_5stage/output/rv32ui-p-beq.out emulator/rv32_5stage/output/rv32ui-p-bge.out emulator/rv32_5stage/output/rv32ui-p-bgeu.out emulator/rv32_5stage/output/rv32ui-p-blt.out emulator/rv32_5stage/output/rv32ui-p-bltu.out emulator/rv32_5stage/output/rv32ui-p-bne.out emulator/rv32_5stage/output/rv32ui-p-fence_i.out emulator/rv32_5stage/output/rv32ui-p-jal.out emulator/rv32_5stage/output/rv32ui-p-jalr.out emulator/rv32_5stage/output/rv32ui-p-j.out emulator/rv32_5stage/output/rv32ui-p-lb.out emulator/rv32_5stage/output/rv32ui-p-lbu.out emulator/rv32_5stage/output/rv32ui-p-lh.out emulator/rv32_5stage/output/rv32ui-p-lhu.out emulator/rv32_5stage/output/rv32ui-p-lui.out emulator/rv32_5stage/output/rv32ui-p-lw.out emulator/rv32_5stage/output/rv32ui-p-ori.out emulator/rv32_5stage/output/rv32ui-p-or.out emulator/rv32_5stage/output/rv32ui-p-sb.out emulator/rv32_5stage/output/rv32ui-p-sh.out emulator/rv32_5stage/output/rv32ui-p-simple.out emulator/rv32_5stage/output/rv32ui-p-slli.out emulator/rv32_5stage/output/rv32ui-p-sll.out emulator/rv32_5stage/output/rv32ui-p-slti.out emulator/rv32_5stage/output/rv32ui-p-slt.out emulator/rv32_5stage/output/rv32ui-p-srai.out emulator/rv32_5stage/output/rv32ui-p-sra.out emulator/rv32_5stage/output/rv32ui-p-sub.out emulator/rv32_5stage/output/rv32ui-p-sw.out emulator/rv32_5stage/output/rv32ui-p-xori.out emulator/rv32_5stage/output/rv32ui-p-xor.out emulator/rv32_5stage/output/towers.riscv.out emulator/rv32_5stage/output/vvadd.riscv.out emulator/rv32_ucode/output/dhrystone.riscv.out emulator/rv32_ucode/output/median.riscv.out emulator/rv32_ucode/output/multiply.riscv.out emulator/rv32_ucode/output/qsort.riscv.out emulator/rv32_ucode/output/rv32mi-p-sbreak.out emulator/rv32_ucode/output/rv32mi-p-scall.out emulator/rv32_ucode/output/rv32ui-p-addi.out emulator/rv32_ucode/output/rv32ui-p-add.out emulator/rv32_ucode/output/rv32ui-p-andi.out emulator/rv32_ucode/output/rv32ui-p-and.out emulator/rv32_ucode/output/rv32ui-p-auipc.out emulator/rv32_ucode/output/rv32ui-p-beq.out emulator/rv32_ucode/output/rv32ui-p-bge.out emulator/rv32_ucode/output/rv32ui-p-bgeu.out emulator/rv32_ucode/output/rv32ui-p-blt.out emulator/rv32_ucode/output/rv32ui-p-bltu.out emulator/rv32_ucode/output/rv32ui-p-bne.out emulator/rv32_ucode/output/rv32ui-p-fence_i.out emulator/rv32_ucode/output/rv32ui-p-jal.out emulator/rv32_ucode/output/rv32ui-p-jalr.out emulator/rv32_ucode/output/rv32ui-p-j.out emulator/rv32_ucode/output/rv32ui-p-lb.out emulator/rv32_ucode/output/rv32ui-p-lbu.out emulator/rv32_ucode/output/rv32ui-p-lh.out emulator/rv32_ucode/output/rv32ui-p-lhu.out emulator/rv32_ucode/output/rv32ui-p-lui.out emulator/rv32_ucode/output/rv32ui-p-lw.out emulator/rv32_ucode/output/rv32ui-p-ori.out emulator/rv32_ucode/output/rv32ui-p-or.out emulator/rv32_ucode/output/rv32ui-p-sb.out emulator/rv32_ucode/output/rv32ui-p-sh.out emulator/rv32_ucode/output/rv32ui-p-simple.out emulator/rv32_ucode/output/rv32ui-p-slli.out emulator/rv32_ucode/output/rv32ui-p-sll.out emulator/rv32_ucode/output/rv32ui-p-slti.out emulator/rv32_ucode/output/rv32ui-p-slt.out emulator/rv32_ucode/output/rv32ui-p-srai.out emulator/rv32_ucode/output/rv32ui-p-sra.out emulator/rv32_ucode/output/rv32ui-p-sub.out emulator/rv32_ucode/output/rv32ui-p-sw.out emulator/rv32_ucode/output/rv32ui-p-xori.out emulator/rv32_ucode/output/rv32ui-p-xor.out emulator/rv32_ucode/output/towers.riscv.out emulator/rv32_ucode/output/vvadd.riscv.out > test-results.xml
grep CPI emulator/rv32_1stage/output/.out
make: [rv32_1stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_2stage/output/.out
make: [rv32_2stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_3stage/output/.out
make: [rv32_3stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_5stage/output/.out
make: [rv32_5stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_ucode/output/.out
make: [rv32_ucode-report-cpi] Error 1 (ignored)
grep Acc emulator/rv32_1stage/output/.out
make: [rv32_1stage-report-bp] Error 1 (ignored)
grep Acc emulator/rv32_2stage/output/.out
make: [rv32_2stage-report-bp] Error 1 (ignored)
grep Acc emulator/rv32_3stage/output/.out
make: [rv32_3stage-report-bp] Error 1 (ignored)
grep Acc emulator/rv32_5stage/output/.out
make: [rv32_5stage-report-bp] Error 1 (ignored)
grep Acc emulator/rv32_ucode/output/.out
make: [rv32_ucode-report-bp] Error 1 (ignored)
grep "#" emulator/rv32_1stage/output/.out
make: [rv32_1stage-report-stats] Error 1 (ignored)
grep "#" emulator/rv32_2stage/output/.out
make: [rv32_2stage-report-stats] Error 1 (ignored)
grep "#" emulator/rv32_3stage/output/.out
make: [rv32_3stage-report-stats] Error 1 (ignored)
grep "#" emulator/rv32_5stage/output/.out
make: [rv32_5stage-report-stats] Error 1 (ignored)
grep "#" emulator/rv32_ucode/output/.out
make: [rv32_ucode-report-stats] Error 1 (ignored)

rv32_3stage build failure on Ubuntu 17.04

Hi,

I'm trying to build following the build instructions, and the emulator build failed with the following messages; Could you please let me know where/which file to look into?
From the message I can see it's somewhere in risc-v code itself or Chisel, but there is no emulator/rv32_3stages/generated-src path/file & no other informative message, so I don't know where to look into.

I use Ubuntu 17.04 and created a fresh VM session just for this, then exactly followed the instruction on the page.

[ Error messages ]
<...>
make[1]: Leaving directory '/home/sshimomu/riscv-sodor/emulator/rv32_2stage'
make -C emulator/rv32_3stage/
make[1]: Entering directory '/home/sshimomu/riscv-sodor/emulator/rv32_3stage'
cd /home/sshimomu/riscv-sodor && java -Xmx4096M -Xss8M -XX:MaxPermSize=128M -jar /home/sshimomu/riscv-sodor/sbt/sbt-launch.jar "project rv32_3stage" "run -td emulator/rv32_3stage/generated-src"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=128M; support was removed in 8.0
[info] Loading project definition from /home/sshimomu/riscv-sodor/project
[info] Set current project to riscv-sodor (in build file:/home/sshimomu/riscv-sodor/)
[info] Set current project to rv32_3stage (in build file:/home/sshimomu/riscv-sodor/)
[info] Running Sodor.elaborate -td emulator/rv32_3stage/generated-src
[info] [0.005] Elaborating design...
[error] (run-main) chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
at chisel3.core.requireIsChiselType$.apply(Binding.scala:41)
at chisel3.core.Output$.apply(Data.scala:176)
at Sodor.CtrlSignals.(cpath.scala:34)
at Sodor.CpathIo.(cpath.scala:46)
at Sodor.CtlPath.(cpath.scala:53)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at chisel3.core.Module$.do_apply(Module.scala:45)
at Sodor.Core.(core.scala:26)
[info] Set current project to rv32_3stage (in build file:/home/sshimomu/riscv-sodor/)
[info] Running Sodor.elaborate -td emulator/rv32_3stage/generated-src
[info] [0.005] Elaborating design...
[error] (run-main) chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
at chisel3.core.requireIsChiselType$.apply(Binding.scala:41)
at chisel3.core.Output$.apply(Data.scala:176)
at Sodor.CtrlSignals.(cpath.scala:34)
at Sodor.CpathIo.(cpath.scala:46)
at Sodor.CtlPath.(cpath.scala:53)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at chisel3.core.Module$.do_apply(Module.scala:45)
at Sodor.Core.(core.scala:26)
[info] Set current project to rv32_3stage (in build file:/home/sshimomu/riscv-sodor/)
[info] Running Sodor.elaborate -td emulator/rv32_3stage/generated-src
[info] [0.005] Elaborating design...
[error] (run-main) chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
chisel3.core.Binding$ExpectedChiselTypeException: 'chisel3.core.UInt@2a9' must be a Chisel type, not hardware
at chisel3.core.requireIsChiselType$.apply(Binding.scala:41)
at chisel3.core.Output$.apply(Data.scala:176)
at Sodor.CtrlSignals.(cpath.scala:34)
at Sodor.CpathIo.(cpath.scala:46)
at Sodor.CtlPath.(cpath.scala:53)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at Sodor.Core$$anonfun$2.apply(core.scala:26)
at chisel3.core.Module$.do_apply(Module.scala:45)
at Sodor.Core.(core.scala:26)
$>

Reports or tracing summary

Before that, I can see a tracing summary of the emulation as follows. But now, those summary info are not there anymore. I thought "make reports" would produce something similar, it failed too. I am running sodor on Ubuntu 16.04. Do you have solution for that, for example, change some emulation flag or fix of script for "make reports"?

Thank you

-bash-4.1$ tail -n 16 output/vvadd.riscv.out
 
#----------- Tracer Data -----------
#
#      CPI   : 1.27
#      IPC   : 0.79
#      cycles: 3426
#
#      Bubbles     : 20.957 %
#      Nop instr   : 0.000 %
#      Arith instr : 37.916 %
#      Ld/St instr : 30.385 %
#      branch instr: 9.982 %
#      misc instr  : 0.759 %
#-----------------------------------

*** PASSED ***
-bash-4.1$

`make reports` errors:

.....
de/output/rv32ui-p-lh.out emulator/rv32_ucode/output/rv32ui-p-fence_i.out emulator/rv32_ucode/output/rv32ui-p-bne.out emulator/rv32_ucode/output/towers.riscv.out > test-results.xml
grep CPI emulator/rv32_1stage/output/*.out
Makefile:83: recipe for target 'rv32_1stage-report-cpi' failed
make: [rv32_1stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_2stage/output/*.out
Makefile:83: recipe for target 'rv32_2stage-report-cpi' failed
make: [rv32_2stage-report-cpi] Error 1 (ignored)
grep CPI emulator/rv32_3stage/output/*.out
.....

syntax errors while building

Hello,

I'm trying to build according instructions and I get following errors:

`g++ -O1 -std=c++11 -g -I/home/zhani/riscv-sodor/emulator/common -I/usr/local/include -Igenerated-src -c -o htif_emulator.o /home/zhani/riscv-sodor/emulator/common/htif_emulator.cc

In file included from /home/zhani/riscv-sodor/emulator/common/htif_emulator.cc:1:0:
/home/zhani/riscv-sodor/emulator/common/htif_emulator.h: In constructor ‘htif_emulator_t::htif_emulator_t(uint64_t, const std::vector<std::__cxx11::basic_string >&)’:
/home/zhani/riscv-sodor/emulator/common/htif_emulator.h:19:32: error: ‘assert’ was not declared in this scope
assert ((memsz >> 20) > 0);
^

/home/zhani/riscv-sodor/emulator/common/htif_emulator.h: In member function ‘void htif_emulator_t::set_clock_divisor(int, int)’:
/home/zhani/riscv-sodor/emulator/common/htif_emulator.h:24:51: error: ‘write_cr’ was not declared in this scope
write_cr(-1, 63, divisor | hold_cycles << 16);
^

/home/zhani/riscv-sodor/emulator/common/htif_emulator.cc: In member function ‘void htif_emulator_t::tick(bool, bool, bool, uint64_t, bool, uint64_t)’:
/home/zhani/riscv-sodor/emulator/common/htif_emulator.cc:41:7: error: ‘packet_header_t’ was not declared in this scope
packet_header_t ack(HTIF_CMD_ACK, seqno, 1, 0);
^
`

I grepped write_cr and it's only found at that 1 location, how is this supposed to compile?

make run-emulator fails

Hi,

I get the below errors while building. Please help solving them.

http://pastebin.com/zbTwyisc

Exotics CompArch

Is it possible to add some sample exotic architectures like

Transport Triggered Architectures
Wave front / Wave scaler
Systolic Array
Dataflow
etc.

They don't have to be comprehensive but something for say graduate level study and research.

ERROR: Active region did not converge when run simulation

Instantiated DTM.
%Error: generated-src/Top.v:3512: Active region did not converge.
Aborting...

64 bit MStatus for RV32I?

Hi,
When I read the code csr.scala inside riscv-sodor/src/common, I found that Mstatus has 64 bit.
It might be a legacy from rocket, and wouldn't it cause problem for RV32I?

Bug in 3-stage ALU sltu instruction?

It seems that the isSLTU function checks if the least significant bit is set to distinguish between SLT and SLTU. However, they are encoded as 12 and 14 respectively, so SLTU is executed as SLT. Checking bit 1 instead would seem to fix this?

make run-tmulator fails

I am getting following error in "make run-emulator"

verilator --cc --exe --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor/vsrc -O3 -CFLAGS " -O1 -std=c++11 -g -I/home/farhad/Downloads/riscv-sodor/emulator/common -I/usr/local/include -I/home/farhad/Downloads/riscv-sodor/riscv-fesvr/fesvr -L/usr/local/lib -Wl,-rpath,/usr/local/lib -L. -lpthread -DVERILATOR -include /home/farhad/Downloads/riscv-sodor/emulator/common/verilator.h"
-o /home/farhad/Downloads/riscv-sodor/emulator/rv32_1stage/emulator generated-src/Top.v /home/farhad/Downloads/riscv-sodor/vsrc/SimDTM.v -LDFLAGS " -L/usr/local/lib -Wl,-rpath,/usr/local/lib -L. -lpthread" /home/farhad/Downloads/riscv-sodor/emulator/common/emulator.cpp /home/farhad/Downloads/riscv-sodor/riscv-fesvr/build/libfesvr.so /home/farhad/Downloads/riscv-sodor/emulator/rv32_1stage/SimDTM.o
%Error: generated-src/Top.v:3748: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER
%Error: generated-src/Top.v:4254: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER
%Error: generated-src/Top.v:4741: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER
%Error: Exiting due to 3 error(s)
%Error: Command Failed /usr/bin/verilator_bin --cc --exe --top-module Top '+define+PRINTF_COND=1' --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor/vsrc -O3 -CFLAGS ' -O1 -std=c++11 -g -I/home/farhad/Downloads/riscv-sodor/emulator/common -I/usr/local/include -I/home/farhad/Downloads/riscv-sodor/riscv-fesvr/fesvr -L/usr/local/lib -Wl,-rpath,/usr/local/lib -L. -lpthread -DVERILATOR -include /home/farhad/Downloads/riscv-sodor/emulator/common/verilator.h' -o /home/farhad/Downloads/riscv-sodor/emulator/rv32_1stage/emulator generated-src/Top.v /home/farhad/Downloads/riscv-sodor/vsrc/SimDTM.v -LDFLAGS ' -L/usr/local/lib -Wl,-rpath,/usr/local/lib -L. -lpthread' /home/farhad/Downloads/riscv-sodor/emulator/common/emulator.cpp /home/farhad/Downloads/riscv-sodor/riscv-fesvr/build/libfesvr.so /home/farhad/Downloads/riscv-sodor/emulator/rv32_1stage/SimDTM.o
/home/farhad/Downloads/riscv-sodor/emulator/common/Makefile.include:103: recipe for target 'emulator' failed
make[1]: *** [emulator] Error 10
make[1]: Leaving directory '/home/farhad/Downloads/riscv-sodor/emulator/rv32_1stage'
Makefile:108: recipe for target 'emulator/rv32_1stage/emulator' failed
make: *** [emulator/rv32_1stage/emulator] Error 2

Can someone tell me a solution for this error?

README bare metal and pk start addresses

The README lists the start addresses for bare metal and pk programs as at 0x2000 and 0x10000 respectively. Is there an extra 0 appended on there? Other documentation I've seen list 0x200 and 0x1000 and that's what the benchmarks committed to this repo also have.

Clone of '[email protected]:riscv/riscv-fesvr.git' into submodule path 'riscv-fesvr' failed

I think github no longer supports git@github. It needs https:// or ssh:// urls.

$ git submodule update --init --recursive
Cloning into 'riscv-fesvr'...
Saving password to keychain failed
Permission denied (publickey).
fatal: Could not read from remote repository.

Please make sure you have the correct access rights
and the repository exists.
Clone of '[email protected]:riscv/riscv-fesvr.git' into submodule path 'riscv-fesvr' failed

HTIF documentation

Is there any documentation on what the HTIF ports actually are and how to use them? For example the CSR ports seem to be command ports, mem ports memory ports, which would imply the ipi ports are instruction ports. But if the ipi ports are instruction ports, how are we supposed to load instructions for it when all of its ports are only one bit wide? And so on.

hi

Dear Sodor Team,
I'm working to test sodor processor for some work, and I got the following error when I tried to compile the tests,,,, in order to write a new test for me

/riscv-sodor/riscv-tests/isa$ make
riscv32-unknown-elf-gcc -m32 -DENTROPY=7542 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -I./../env/p -I./macros/scalar -T./../env/p/link.ld rv32ui/simple.S -o rv32ui-p-simple
rv32ui/simple.S: Assembler messages:
rv32ui/simple.S:16: Error: unrecognized opcode mrts' rv32ui/simple.S:16: Error: Instruction csrw requires absolute expression rv32ui/simple.S:16: Error: Instruction csrr requires absolute expression rv32ui/simple.S:16: Error: unrecognized opcodeeret'
make: *** [rv32ui-p-simple] Error 1

can you please advice??

How to compile the tracer?

I was looking at the emulator/common/Makefile.include and it turns out that the code for building the tracer is commented out. Additionally, it looks like tracer.cpp includes "emulator.h" which I couldn't find in the source code. Would you please let me know how I can build the tracer so that I can get the trace information in the outputs?

Implementing rv64 for the sodor core: Purpose of SodorScratchpadAdapter's restriction to 32-bit addresses?

I am trying port the sodor core to rv64 -- However, I am stumbling upon the line with hardcoded size of 32-bits:

require(io.slavePort.req.bits.addr.getWidth == 32, "Slave port only support 32 bit address")

in generators/riscv-sodor/src/main/scala/sodor/common/scratchpad_adapter.scala, class SodorScratchpadAdapter.

Could you point to more documentation regarding the adapter and the reason behind this line of code? A simple XLEN and SystemBusKey change in the sodor core triggered this assertion -- but I struggle to find the context behind the adapter's restriction to a 32-bit wide address.

race condition in SimDTM.v under Verilator; related to "taddr-4" in fesvr/dtm.cc, write_chunk

vsrc/SimDTM.v contains this call to debug_tick:

      __exit = debug_tick(
        __debug_req_valid,
        __debug_req_ready,
        __debug_req_bits_addr,
        __debug_req_bits_op,
        __debug_req_bits_data,
        __debug_resp_valid,
        __debug_resp_ready,
        __debug_resp_bits_resp,
        __debug_resp_bits_data
      );

This reads inputs, such as __debug_req_valid, that may depend on its own outputs, such as __debug_resp_valid. This makes the circuit behavior undefined.

There are existing code lines that attempt to solve this by introducing delays, for example:

  assign #0.1 debug_req_valid = __debug_req_valid;

but the delay specifier ("#0.1") has no effect under Verilator.

One way to make this race condition visible is to add a diagnostic printout to debug.scala:

diff --git a/src/common/debug.scala b/src/common/debug.scala
index ead55bc..b21d391 100644
--- a/src/common/debug.scala
+++ b/src/common/debug.scala
@@ -169,6 +169,32 @@ class DebugModule(implicit val conf: SodorConfiguration) extends Module {
   dmstatus.allhalted := dmcontrol.haltreq
   dmstatus.allrunning := dmcontrol.resumereq
   io.dcpath.halt := dmstatus.allhalted && !dmstatus.allrunning
+
+  // Stronger condition.
+  val outercond =
+    ( (io.dmi.req.bits.op === DMConsts.dmi_OP_WRITE) &&
+      (decoded_addr(DMI_RegAddrs.DMI_COMMAND)) &&
+      io.dmi.req.valid );
+
+  // Weaker condition.  I call this "inner" because its two elements are
+  // syntactically contained inside the "outer" condition.
+  val innercond = 
+    ( (decoded_addr(DMI_RegAddrs.DMI_COMMAND)) &&
+      io.dmi.req.valid );
+
+  // This creates an extra use of 'innercond' that changes the way
+  // Verilator generates code.  It is needed to expose the bug.  The
+  // value also has to be used somewhere, which is why it appears in
+  // the "bug happened" printout below.
+  val anothercond = innercond && dmcontrol.haltreq;
+
+  // Test for the impossible combination.
+  when (outercond) {
+    when (!innercond) {
+      printf("bug happened! anothercond=%d\n", anothercond);
+    }
+  }
+
   when (io.dmi.req.bits.op === DMConsts.dmi_OP_WRITE){
     when((decoded_addr(DMI_RegAddrs.DMI_ABSTRACTCS)) && io.dmi.req.valid) {
       val tempabstractcs = wdata.asTypeOf(new ABSTRACTCSFields())

With the above change, we see printouts indicating the impossible condition happens:

emulator/rv32_1stage$ ./emulator +max-cycles=30000 ../../install/riscv-tests/rv32ui-p-simple
Instantiated DTM.
bug happened! anothercond=0
bug happened! anothercond=0
bug happened! anothercond=0
bug happened! anothercond=0
Cyc=          0 [1] pc=[80000000] W[r 0=80000004][1] Op1=[r 0][00000000] Op2=[r12][00000000] inst=[04c0006f]  J  DASM(04c0006f)
[...]

At first I thought this was a bug in Verilator and filed verilator/verilator#2177 for it, but was informed about the race condition in SimDTM.v, so I'm reporting it here.

To fix the bug, I propose (following the advice in the linked issue):

diff --git a/vsrc/SimDTM.v b/vsrc/SimDTM.v
index a5f8c23..1d968d6 100644
--- a/vsrc/SimDTM.v
+++ b/vsrc/SimDTM.v
@@ -46,12 +46,18 @@ module SimDTM(
   bit __debug_resp_ready;
   int __exit;
 
-  assign #0.1 debug_req_valid = __debug_req_valid;
-  assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0];
-  assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0];
-  assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0];
-  assign #0.1 debug_resp_ready = __debug_resp_ready;
-  assign #0.1 exit = __exit;
+  // Copy data from 'debug_tick' on the negative clock edge so it does
+  // not happen at the same time as a positive clock edge, which would
+  // create a dependency cycle.
+  always @(negedge clk)
+  begin
+    debug_req_valid     <= __debug_req_valid;
+    debug_req_bits_addr <= __debug_req_bits_addr[6:0];
+    debug_req_bits_op   <= __debug_req_bits_op[1:0];
+    debug_req_bits_data <= __debug_req_bits_data[31:0];
+    debug_resp_ready    <= __debug_resp_ready;
+    exit                <= __exit;
+  end
 
   always @(posedge clk)
   begin

That change eliminates the observed misbehavior in debug.scala. However, tests then fail. For example:

emulator/rv32_1stage$ ./emulator +max-cycles=30000 ../../install/riscv-tests/rv32ui-p-simple
Instantiated DTM.
Cyc=          0 [1] pc=[80000000] W[r30=00000002][1] Op1=[r 0][00000000] Op2=[r 2][00000000] inst=[34202f73]     DASM(34202f73)
[...]
Cyc=      29714 [1] pc=[00000060] W[r 5=00000060][1] Op1=[r 0][00000000] Op2=[r 0][00000060] inst=[00000297]     DASM(00000297)
*** FAILED *** (timeout) after 30000 cycles

The problem now is that the program does not get loaded correctly. The first instruction should be 0x04c0006f, not 0x34202f73, which is the second instruction. I tracked this down to riscv-isa-sim/fesvr/dtm.cc, write_chunk, which has this line:

  write(DMI_SBADDRESS0, taddr-4);

The problem is the mysterious -4. There is nothing in the RISCV debug specification to suggest that should be needed (on the contrary, it should not), and there isn't anything similar in read_chunk nor in the non-Sodor implementation of write_chunk. I speculate the -4 was added because it compensated for an effect of the race condition I'm describing. If I remove it, and also fix the race as described above, then programs work again.

Unfortunately, even then not all of the tests pass. The first to fail is rv32_3stage, rv32ui-p-xori:

emulator/rv32_3stage$ ./emulator +max-cycles=30000 ../../install/riscv-tests/rv32ui-p-xori
[...]
Cyc=        280 [1] pc=[80000048] W[r 0=8000004c][1] Op1=[r31][0000000b] Op2=[r25][00000000] inst=[ff9ff06f]     DASM(ff9ff06f)
terminate called after throwing an instance of 'std::runtime_error'
  what():  bad syscall #342274048501219439
Exit 255

I have not attempted to debug that failure yet. I figured I'd file what I have and get some feedback before going further.

make run-emulator FAILED

Hi
when i make run-emulator i had pass in rv32_1stage rv32_2stage rv32_5stage but met the follow error in rv32_ucode
make[1]: [output/xori.out] Error 255 (ignored)
[ FAILED ] output/simple.out (timeout) after 30000 cycles
[ FAILED ] output/add.out (timeout) after 30000 cycles
[ FAILED ] output/addi.out (timeout) after 30000 cycles
[ FAILED ] output/and.out (timeout) after 30000 cycles
[ FAILED ] output/andi.out (timeout) after 30000 cycles
[ FAILED ] output/auipc.out (timeout) after 30000 cycles
[ FAILED ] output/beq.out (timeout) after 30000 cycles
[ FAILED ] output/bge.out (timeout) after 30000 cycles
[ FAILED ] output/bgeu.out (timeout) after 30000 cycles
then i checked /emulator/rv32_ucode/output/***.out find
Loaded memory.
Instantiated HTIF.
Cyc= 0 PCReg=( 0x00000000 ) InstReg=[ 0x00000000 : unknown ] UPC= 6 (MA=0x0000eeee) RegAddr=32 Bus=0x00002000 A=0x0000aaaa B=0x0000bbbb
all PCreg is zero
how can i solve this problem?

The encoding of stall instruction is incorrect in the emulator

The stall instruction used (XOR x0 x0 x0) is encoded as 0x4033, however, in trace.c and bp.cpp, 0x5033 is used (which is also no-ops). it however causes the incorrect summary output for Bubbles percentage in examples such as output/vvadd.riscv.out.

To fix: change 5033 to 4033 in trace.c and bp.cpp

csignals lookup table has wrong op1 and op2 sel for JALR.

I notice the csignals lookup table has incorrect definition of the op1sel and op2sel signals:

JALR -> List(Y, BR_JR , OP1_RS1, OP2_IMI , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N),
Should be:

JALR -> List(Y, BR_JR , OP1_X, OP2_X , ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, CSR.N),

I have not been building riscv-sodor so I can imagine this makes no difference, the ALU result is discarded for JALR anyway.

It just confused me for a while as I'm writing my own Sodar 1-Stage in SpinalHDL and peeking at your csignals table to check I had got mine right.

I get the following error while executing a simulation of the Sodor 1-stage processor running the Towers of Hanoi benchmark

phillips@ubuntu:~/COMPUTER_ORGANIZATION/chipyard_root/chipyard/sims/verilator$ make CONFIG=Sodor1StageConfig run-binary BINARY=${BMARKS}/towers.riscv
Running with RISCV=/home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/riscv-tools-install
(set -o pipefail && /home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/sims/verilator/simulator-chipyard-Sodor1StageConfig +permissive +dramsim +dramsim_ini_dir=/home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/generators/testchipip/src/main/resources/dramsim2_ini +max-cycles=10000000 +verbose +permissive-off /towers.riscv </dev/null 2> >(spike-dasm > /home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/sims/verilator/output/chipyard.TestHarness.Sodor1StageConfig/towers.out) | tee /home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/sims/verilator/output/chipyard.TestHarness.Sodor1StageConfig/towers.log)
[UART] UART0 is here (stdin/stdout).
make: *** [/home/phillips/COMPUTER_ORGANIZATION/chipyard_root/chipyard/common.mk:162: run-binary] Error 255

5-stage - JAL rd use bug

Dependent instructions are not properly stalled that depend on a JAL instruction.

elf2hex usage with sodor ( assertion `taddr < width*depth' failed )

I am trying to use elf2hex utility on a host ( little endian x86_64).
In the riscv-sodor/riscv-tests/benchmarks

I do:

make riscv

Then i try to convert the dhrystone.riscv ( generated by riscv32-unknown-elf-gcc ) to hex :

elf2hex 16 32768 dhrystone.riscv

i get :

elf2hex: ./fesvr/htif_hexwriter.cc:16: virtual void htif_hexwriter_t::read_chunk(addr_t, size_t, void*): Assertion `taddr < width*depth` failed.

I also tried other width and length but i always get this assertion.

Can someone please let me know what can be the issue.

Data memory mem_rw and mem_val

Hi, I'm trying to understand riscv-sodor microarchitecture and I have a doubt about the data memory. What are the functions of mem_val and mem_rw input signals?

why is this named after the beloved island home of thomas the tank engine and friends?

not an issue, i'm just curious.

Stalling in 3-stage SODOR

I just wanted to clarify something, looking at the 3-stage SODOR source code I see stalling present for data hazards, but nothing that seems to respond to memory. Am I correct in assuming that SODOR assumes a single cycle response for memory operations or something therein?

Out of time during test rv32ui-p-simple

Errors when run make run-emulator

> make run-emulator            

running basedir/Makefile: make run-emulator

make -C emulator/rv32_1stage/ run
make[1]: Entering directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage'
make -C /home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/fesvr libfesvr.a
make[2]: Entering directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/fesvr'
make[2]: 'libfesvr.a' is up to date.
make[2]: Leaving directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/fesvr'
verilator --cc --exe  --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/phantom/mychip/riscv-sodor/vsrc -O3 -CFLAGS "-O1 -std=c++11 -g -I/home/phantom/mychip/riscv-sodor/emulator/common -I/home/phantom/mychip/riscv-sodor/riscv-isa-sim -DVERILATOR -include /home/phantom/mychip/riscv-sodor/emulator/common/verilator.h" -LDFLAGS " /home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/fesvr/libfesvr.a -lpthread" -o /home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/emulator generated-src/Top.v /home/phantom/mychip/riscv-sodor/vsrc/SimDTM.v /home/phantom/mychip/riscv-sodor/emulator/common/emulator.cpp /home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/SimDTM.o
make -C /home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/obj_dir -f VTop.mk
make[2]: Entering directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/obj_dir'
make[2]: Nothing to be done for 'default'.
make[2]: Leaving directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage/obj_dir'
./emulator +max-cycles=30000 /home/phantom/mychip/riscv-sodor/install/riscv-tests/rv32ui-p-simple 3>&1 1>&2 2>&3 | /home/phantom/mychip/riscv-sodor/emulator/common/tracer.py > output/rv32ui-p-simple.out
/home/phantom/mychip/riscv-sodor/emulator/common/Makefile.include:215: recipe for target 'output/rv32ui-p-simple.out' failed
make[1]: *** [output/rv32ui-p-simple.out] Error 255
make[1]: Leaving directory '/home/phantom/mychip/riscv-sodor/emulator/rv32_1stage'
Makefile:99: recipe for target 'emulator/rv32_1stage/generated-src/timestamp' failed
make: *** [emulator/rv32_1stage/generated-src/timestamp] Error 2

Following is the part of the result from ./emulator +max-cycles=30000 /home/phantom/mychip/riscv-sodor/install/riscv-tests/rv32ui-p-simple

...
Cyc=      29705 [1] pc=[80000024] W[r 8=00000000][0] Op1=[r30][fffffffc] Op2=[r 0][00000000] inst=[000f0463]     DASM(000f0463)
Cyc=      29706 [1] pc=[80000028] W[r 0=8000002c][1] Op1=[r30][fffffffc] Op2=[r 0][00000000] inst=[000f0067]  R  DASM(000f0067)
Cyc=      29707 [1] pc=[fffffffc] W[r 0=00000000][1] Op1=[r 0][00000000] Op2=[r12][00000000] inst=[04c0006f]  J  DASM(04c0006f)
Cyc=      29708 [1] pc=[00000048] W[r10=00000000][1] Op1=[r 0][00000000] Op2=[r20][00000000] inst=[f1402573]     DASM(f1402573)
Cyc=      29709 [1] pc=[0000004c] W[r 0=00000000][0] Op1=[r10][00000000] Op2=[r 0][00000000] inst=[00051063]     DASM(00051063)
Cyc=      29710 [1] pc=[00000050] W[r 5=00000050][1] Op1=[r 0][00000000] Op2=[r 0][00000050] inst=[00000297]     DASM(00000297)
Cyc=      29711 [1] pc=[00000054] W[r 5=00000060][1] Op1=[r 5][00000050] Op2=[r16][00000010] inst=[01028293]     DASM(01028293)
Cyc=      29712 [1] pc=[00000058] W[r 0=00000100][1] Op1=[r 5][00000060] Op2=[r 5][00000060] inst=[30529073]     DASM(30529073)
Cyc=      29713 [1] pc=[0000005c] W[r 0=00000000][1] Op1=[r 0][00000000] Op2=[r 0][00000000] inst=[18005073]     DASM(18005073)
Cyc=      29714 [1] pc=[00000060] W[r 5=00000060][1] Op1=[r 0][00000000] Op2=[r 0][00000060] inst=[00000297]     DASM(00000297)
*** FAILED *** (timeout) after 30000 cycles