Comments (2)
ccelio
commented on August 30, 2024
The tracer stuff is fully deprecated -- it was C++ code that hooked into the C++ testharness designed for students who were familiar with C++. But trying to hook into the RTL signals via C++ code was just too hacky and fragile.
Going forward, I believe the best option is to move the tracer stuff into Chisel so it is synthesizable.
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MahdiNazemi
commented on August 30, 2024
Thanks for your explanation. I will issue a pull request in case I implement a tracer in Chisel, so that it can be integrated in the tool.
from riscv-sodor.
Related Issues (20)
- syntax errors while building HOT 2
- Bug in 3-stage ALU sltu instruction? HOT 2
- rv32_3stage build failure on Ubuntu 17.04 HOT 2
- setup error HOT 2
- Why is it necessary to use RISCV_LINK_OPTS for compilation?
- csignals lookup table has wrong op1 and op2 sel for JALR. HOT 1
- Data memory mem_rw and mem_val
- Reports or tracing summary
- Build error verilator HOT 2
- error when compile riscv-sodor/riscv-tests/benchmarks with XLEN=32
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- race condition in SimDTM.v under Verilator; related to "taddr-4" in fesvr/dtm.cc, write_chunk
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- make run emulator error HOT 8
- why is this named after the beloved island home of thomas the tank engine and friends? HOT 1
- No emulator directory?? HOT 2
- I get the following error while executing a simulation of the Sodor 1-stage processor running the Towers of Hanoi benchmark HOT 2
- ERROR: Active region did not converge when run simulation
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