olofk / corescore Goto Github PK

It would be nice to be able to test a variety of different cores, like VeeRwolf to see how they fit in a given device.
This would allow you to demonstrate the impressive size of SERV by showing how many more copies fit in an FPGA compared to other common RISC-V cores.

A meta issue to collect all the things we want to implement for CoreScore 2.0

• A ring bus to replace the mux
• Move memory out from corescorecore to easier allow several instances to share one memory
• Use a newer version of SERV

I'm running corescore straight out of the box with a clean install. (Or at least, I think it's clean, because the whole dependency chain is very opaque to me.)

I get the following error:

fusesoc run --target=intel_max10_devkit corescore
...
Error (12002): Port "i_wb_rst" does not exist in macrofunction "ram" File: /home/tom/projects/corescore_ws/build/corescore_0/src/corescore_0/rtl/emitter.v Line: 128

In ~/projects/corescore_ws/build/corescore_0/src/corescore_0/rtl/emitter.v, I indeed see the following:

   servant_ram
     #(.memfile (memfile),
       .depth (memsize))
   ram
     (// Wishbone interface
      .i_wb_clk (i_clk),
      .i_wb_rst (i_rst),              <<<<<<<<<<<<<<
      .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
      .i_wb_cyc (wb_mem_cyc),
      .i_wb_we  (wb_mem_we) ,
      .i_wb_sel (wb_mem_sel),
      .i_wb_dat (wb_mem_dat),
      .o_wb_rdt (wb_mem_rdt),
      .o_wb_ack (wb_mem_ack));

And in /home/tom/projects/corescore_ws/build/corescore_0/src/serving_1.0.2/serving/serving_ram.v, I see:

module serving_ram
  #(//Memory parameters
    parameter depth = 256,
    parameter aw    = $clog2(depth),
    parameter memfile = "")
   (input wire          i_clk,
    input wire [aw-1:0] i_waddr,
    input wire [7:0]    i_wdata,
    input wire          i_wen,
    input wire [aw-1:0] i_raddr,
    output wire [7:0]   o_rdata,

    input wire [aw-1:2] i_wb_adr,
    input wire [31:0]   i_wb_dat,
    input wire [3:0]    i_wb_sel,
    input wire          i_wb_we,
    input wire          i_wb_stb,
    output wire [31:0]  o_wb_rdt,
    output reg          o_wb_ack);

There is, indeed, no i_wb_rst to be seen in serving_ram. There is also no i_wb_rst in the serving_ram repo.

So how can this possible have ever worked before???
I really want to love fusesoc, but every time I get near it, I get hit with incomprehensible dependency issues.

Tom

Has anyone successfully built corescore with fusesoc 2.2.1?

I've run this with 2.0rc1, but I get:

from fusesoc.capi2.generator import Generator

ModuleNotFoundError: No module named 'fusesoc'

Is there an easy way to downgrade fusesoc?

When trying to run corescore for the Lattice iCE40-HX8K FPGA, I get an error during placement:

ERROR: Unable to find legal placement for all cells, design is probably at utilisation limit. 

I've attached a log file containing the output from fusesoc run --target=hx8k corescore. hx8k.log

Please let me know if I can provide any other information to help identify the issue.

Background: Ran into this thought because I wanted to find out if someone has already run CoreScore on one of the FPGA boards that I wanted to try it on.

Why:

• The intent is to capture available core count and other related statistics for the CoreScore project.
• This could be useful to analyze cores vs specific hardware, core count over time or simply admire the glorious core numbers.
• It would also help compare obtained core count results with other's results (tool version differences etc.)
• Serve as a reference metric for future updates of the project or the core implementation.

How: Probably maintaining a continually updated list based on known CoreScore results would help.

Here's what I've collected so far.
https://gist.github.com/rajesh-s/15cee76a5696ef932e48e06e4aa88fe8

Thanks for reading, please let me know your thoughts on this!

Since this repository utilizes FuseSoC, how to find a submodule is less obvious compared to those using Makefile. For example, corescore/rtl/corescore_tinyfpga_bx.v initializes the module axis_async_fifo, but searching the name in the repo didn't result in anything.

I have noticed that the tinyfpga_bx target depends on two additional packages: usbserial and fusesoc:utils:generators, but the former doesn't contain axis_async_fifo either, and I have no idea how to find the latter.

Please advice. Thanks!

In the corescore.core file the arty_a7_100t target has the following filesets:

filesets: [base, emitter_serv, arty_a7]

However, the rtl (rtl/corescore_arty_a7.v) instantiates the emitter_uart module, not the emitter_serv module.

Changing the rtl to use the emitter_serv with 306 cores resulted in (Vivado 2023.2):

ERROR: [DRC RTSTAT-6] Partial route conflicts: 10447 net(s) have a partial conflict.

Changing the corescore.core file to use the emitter_uart module resulted in a successful corescore of 306 cores.

I installed fusesoc in May 2020 to run corescore. Today, I ran it again, but it failed when compiling for the Trellis target.

The particular error doesn't really matter, but the problem was that my installation used edalize 0.2.0. After a lot of cursing and checking things out, I figured out that manually forcing an edalize 0.2.3 install (pip install edalize==0.2.3) fixed my issue.

Shouldn't there be a requirements.txt file in corescore (or in fusesoc) that forces an up to date dependency tree?

Tom

Trying to run fusesoc run --setup --target=storeypeak corescore results in the following output:

INFO: Preparing ::serv:1.0.2
INFO: Downloading olofk/serv from github
INFO: Preparing ::verilog-axis:0-r3
INFO: Downloading olofk/verilog-axis from github
INFO: Preparing ::servant:1.0.2-r1
INFO: Downloading olofk/serv from github
INFO: Preparing ::serving:1.0.2
INFO: Downloading olofk/serv from github
INFO: Preparing ::corescore:0
INFO: Generating ::corescore-corescorecore_storeypeak:0
ERROR: Setup failed : Cannot find data/storeypeak.tcl in :
        fusesoc_libraries/corescore
        fusesoc_libraries/corescore

It looks like the missing files should have been added in db8e49d but weren't for some reason.

Hi!

I am trying to port the Alhambra board. I am already synthesizing and loading the design.
I would like to know which is the output of the serial port of the design, to see if it is working OK and the baud-rate (to launch corecount.py)

Thx

Title. Why? Because I wanted to see how the OrangeCrab performs: https://store.groupgets.com/products/orangecrab

@olofk - Come on, you know better :-P

I'm trying to add my board opos6ul_sp in the corescore project. but I'm stuck with a $clog2() problem.

ERROR:HDLCompiler:815 - "/…/workspace/build/corescore_0/src/serving_1.0.2/serving/serving.v" Line 42: System function call clog2 is not allowed here
ERROR:HDLCompiler:815 - "/.../workspace/build/corescore_0/src/serving_1.0.2/serving/serving.v" Line 152: System function call clog2 is not allowed here
ERROR:HDLCompiler:598 - "/.../workspace/build/corescore_0/src/serving_1.0.2/serving/serving.v" Line 21: Module <serving> ignored due to previous errors.

$clog2() function is not supported by ISE in local parameters.
Have you got a solution for this problem ? Maybe use yosys as ISE-Frontend ?

Is there a fusesoc configuration to use yosys as ISE frontend ?

Thanks

Error (170012): Fitter requires 1420 LABs to implement the design, but the device contains only 1395 LABs

I managed to synthesize corescore for colorlight_5a75b. Seems to works but if I open terminal on uart I have an end of line problem :

$ screen /dev/ttyUSB0 57600
  �Core 00002 says hello
                        �Core 00003 says hello
                                              �Core 00004 says hello
                                                                    �Core 00006 says hello
                                                                                          �Core 00007 says hello

I tried to use corecount.py script instead of standard uart terminal but I have an exception on msgpack:

$ python ./fusesoc_libraries/corescore/sw/corecount.py /dev/ttyUSB0
Traceback (most recent call last):
  File "./fusesoc_libraries/corescore/sw/corecount.py", line 50, in <module>
    curses.wrapper(main)
  File "/usr/local/lib/python3.7/curses/__init__.py", line 102, in wrapper
    return func(stdscr, *args, **kwds)
  File "./fusesoc_libraries/corescore/sw/corecount.py", line 39, in main
    u = umsgpack.unpack(ser)
  File "/home/user/pyenv/envp37/lib/python3.7/site-packages/msgpack/__init__.py", line 58, in unpack
    return unpackb(data, **kwargs)
  File "msgpack/_unpacker.pyx", line 211, in msgpack._unpacker.unpackb
msgpack.exceptions.UnpackValueError: Unpack failed: error = 0

My python version is :

$ python --version
Python 3.7.4