vpetry Goto Github PK

attennorm

Attentive Normalization for Conditional Image Generation

bus_pirate

Community driven firmware and hardware for Bus Pirate version 3 and 4

cmsdk_ahb_busmatrix

practice configure AHB-Lite bus protocol

corescore

CoreScore

cython

The most widely used Python to C compiler

freedom-e-sdk

Open Source Software for Developing on the Freedom E Platform

hidden-networks

leflow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

librenard

Reverse Engineered Sigfox Stack - Library

nox

RISC-V Nox core

openfpga

An Open-source FPGA IP Generator

pirate-swd

Implementation of the SWD protocol using the buspirate to flash the STM32, EFM32 and the NUC1XX chip series. This fork is part of the mchck project

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

pynq-z1_board_files

PYNQ-Z1 board files for Vivado

pyrisc

The Educational RISC-V Toolset in Python

riscv-formal

RISC-V Formal Verification Framework

riscv_mcu_cyclonev

RI5CY core implementation for my master's

riscv_verilator_model

Verilator model for RISCV targets

saleae-swd-analyzer

Serial Wire Debug (SWD) Analyzer for Saleae Logic

uvm-tutorial-for-candy-lovers

Source code repo for UVM Tutorial for Candy Lovers

uvm_uart_example

An UVM example of UART

uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

vivado-boards

vulcan

RISC-V Instruction Set Simulator (Built for education).

wbuart32

A simple, basic, formally verified UART controller

yosys

Yosys Open SYnthesis Suite