Name: Carlos Eduardo
Type: User
Company: RISC-V Ambassador / Red Hat Architect / Independent Developer
Bio: Check my articles on https://carlosedp.medium.com and support me at https://github.com/sponsors/carlosedp
Twitter: carlosedp
Location: Sao Paulo/Brazil
Blog: https://fosstodon.org/@carlosedp
Carlos Eduardo's Projects
A Prometheus Exporter for APC UPS hardware via apcupsd
Prometheus & Grafana docker-compose stack for Raspberry Pi
Eclipse B612
Bitwig Studio Controller scripts
Bladerater
Scala Bleep sample project using ZIO and ZIO-HTTP
Example LED blinking project for your FPGA dev board of choice
About me
Personal Website/Blog - http://carlosedp.com
A Chisel HDL template using Scala Bleep build tool
Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
A Chisel implementation for an FPGA Pin Finder thru UART
Chisel HDL example applications
Chisel HDL Template Repository
Repository for chisel3 testers2 open alpha
Chisel 3: A Modern Hardware Design Language
A RISC-V Core (RV32I) written in Chisel HDL
A tiny POWER Open ISA soft processor written in Chisel
Circuit IR Compilers and Tools
Cluster monitoring stack for clusters based on Prometheus Operator
The canonical source for Kubernetes Operators that are published on OperatorHub.io and part of the default catalog of the Operator Lifecycle Manager.
community-operators metadata backing OpenShift OperatorHub
Container management structure
CoreScore
Erlang Diameter Credit Control (DCCA) OTP Client
Erlang Diameter Credit Control (DCCA) OTP application
DD-WRT Router Monitoring Stack
Erlang Diameter Credit Control Application (DCCA) Server and Client (Discontinued in favor of OTP versions)