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View Code? Open in Web Editor NEWStyle guide enforcement for VHDL
License: GNU General Public License v3.0
Style guide enforcement for VHDL
License: GNU General Public License v3.0
Only basic indent rules exist for for loops. These must be expanded.
This rule will take some work to fix. Trying to pattern match the options will be tricky.
The endiing parenthesis in a multi line type statement should be on it's own line and aligned to the "type" keyword.
For inclusion in continuous integration flows, VSG should be able to output the results in JUnit XML files.
When the rules were placed in their own directory, the rule_ is no longer needed.
It is getting tiring trying to find new rules when I am spending most of my time fixing the issues I have already found. Implement a "fix" option that will correct the issues found.
Named assignments should always be used.
A user may not want one of the default rules.
type [name] is (
t ype [name] is (ELEMENT1.
ELEMENT2
);
should be
t ype [name] is (
ELEMENT1.
ELEMENT2
);
With a line number attribute, all the enumerates can be removed.
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