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996.icu

Repo for counting stars and contributing. Press F to pay respect to glorious developers.

accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

aes_128

AES (Rijndael) IP Core (128 bit version)

ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

aib-phy-hardware

Advanced Interface Bus (AIB) die-to-die hardware open source

alice5

SPIR-V fragment shader GPU core based on RISC-V

alpha64_r10000_superscalar_processor

Alpha64 R10000 Two-Way Superscalar Processor

amba3-vip

amba3 apb/axi vip

amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

amba_axi_ahb_apb

AMBA bus lecture material

amiga2000-gfxcard

MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog

ao486

The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.

apb

APB Logic

arm_soc

async-karin

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

autofpga

A utility for Composing FPGA designs from Peripherals

automatic-verilog

automatic-verilog based on vimscript

awesome-dv

Awesome ASIC design verification

awesome-vhdl

vhdl extension for visual studio code

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi-ddr3

学习AXI接口，以及xilinx DDR3 IP使用

axi-sdcard-high-speed-controller

A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)

axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

axi4_interconnect

AXI总线连接器

axi_master

Generic AXI master stub

axi_mem_if

Simple single-port AXI memory interface

axidmacheck

AXI DMA Check: A utility to measure DMA speeds in simulation

axisfifo

Zynq SoC Linux kernel driver for Xilinx AXI-Stream FIFO IP

basic_cache_core