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Verilog Configurable Cache

License: MIT License

Makefile 5.91% C 1.03% SystemVerilog 2.87% Verilog 83.63% Tcl 1.96% C++ 0.87% Shell 0.55% TeX 3.19%

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[WRITE BACK MODE] Not write to backend memory (flushing cache line) when read miss and dirty data exists in that line.

Hi there,

I'm trying to run the testbench but it seems that when I switch to WRITE-BACK mode (btw changing WRITE_POL in the iob-cache_tb.vh will not change the real cache-memory write policy because WRITE_POL is not passed by the testbench, need to pass this parameter to cache instance), when I read a data and it misses, it will read the data from backend to cache line. However, it seems that if that cache line already has dirty data, it will not flush that and write that to backend. Instead, the dirty data will be directly overwritten and loss. As a result, the test will fail and all the dirty data before read operation will be lost.

I quickly went over the code of this part and did not find any write-dirty-data operation. Not sure if i was getting anything wrong with my environment/configuration.

Could you please also test the write-back mode in iob-cache_tb.v and check the results?

Thank you so much.

Possibility to perform Unit / functional tests on the verilated source files

Hello Community,

I would like to understand the possibility to perform Unit / functional testing on the source files generated after verilation.

What would be the suggestion from the community, if someone has been on this path before? My end goal would be check the test coverage results (unit testing would be first preference, but if it is totally not possible then would not mind to consider functional testing as second option). I am aware of the fact that "a unit can be defined by us" in the context of unit testing.

I could not see any relevant post in the forum.

Thanks in advance.

Add driver documentation support

Add driver documentation support using Doxygen.
Develop an example of Doxygen documentation using iob-lib.

m_axi_rready_int assigned into always @* processes

file read-channel-axi.v

simplify testbench mess

there are a lot of testbenches

the core individual testbenches should be simple and for only a common set of parameters

the point is to show users how they could improve on this testbench and add their own tests

IObundle can do exhaustive tests easily with a CPU

64-bit back-end interface fails

This was reported by Salima

a test case should be created

if the problem exists it should be fixed

can the axi ram we have been using support 64-bits?

`make doc-build-all` does not work

The README says to run make doc-build-all. I consistently get an error about a missing settings64.sh file.

make doc-build DOC=pb;  make doc-build DOC=ug;
make[1]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make fpga-build FPGA_FAMILY=CYCLONEV-GT;  make fpga-build FPGA_FAMILY=XCKU;
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/quartus/CYCLONEV-GT build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "5CGTFD9E5F35C7"
../build.sh: line 5: /nios2eds/nios2_command_shell.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache_0.qxp] Error 127
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/vivado/XCKU build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "xcku040-fbva676-1-c"
../build.sh: line 3: /settings64.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache.edif] Error 1
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: *** [Makefile:31: fpga-build-all] Error 2
make[1]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make fpga-build FPGA_FAMILY=CYCLONEV-GT;  make fpga-build FPGA_FAMILY=XCKU;
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/quartus/CYCLONEV-GT build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "5CGTFD9E5F35C7"
../build.sh: line 5: /nios2eds/nios2_command_shell.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache_0.qxp] Error 127
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/quartus/CYCLONEV-GT'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[2]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache'
make -C ./hardware/fpga/vivado/XCKU build
make[3]: Entering directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
../build.sh "iob_cache" "../../../../submodules/INTERCON/hardware/src/merge.v ../../../../submodules/INTERCON/hardware/src/split.v ../../../../submodules/MEM/hardware/regfile/sp_reg_file/iob_sp_reg_file.v ../../../../submodules/MEM/hardware/ram/2p_ram/iob_2p_ram.v ../../../../submodules/MEM/hardware/fifo/bin_counter.v ../../../../submodules/MEM/hardware/fifo/sfifo/iob_sync_fifo.v ../../../../submodules/MEM/hardware/ram/sp_ram/iob_sp_ram.v ../../../../hardware/src/back-end-axi.v ../../../../hardware/src/back-end-native.v ../../../../hardware/src/cache-control.v ../../../../hardware/src/cache-memory.v ../../../../hardware/src/front-end.v ../../../../hardware/src/iob-cache-axi.v ../../../../hardware/src/iob-cache.v ../../../../hardware/src/onehot-to-bin-encoder.v ../../../../hardware/src/read-channel-axi.v ../../../../hardware/src/read-channel-native.v ../../../../hardware/src/replacement-policy.v ../../../../hardware/src/write-channel-axi.v ../../../../hardware/src/write-channel-native.v" "../../../../submodules/INTERCON/hardware/include ../../../../hardware/include" "DUMMY" "xcku040-fbva676-1-c"
../build.sh: line 3: /settings64.sh: No such file or directory
make[3]: *** [../../fpga.mk:15: iob_cache.edif] Error 1
make[3]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache/hardware/fpga/vivado/XCKU'
make[2]: *** [Makefile:28: fpga-build] Error 2
make[2]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make[1]: *** [Makefile:31: fpga-build-all] Error 2
make[1]: Leaving directory '/home/dbrumley/git/github/iobundle/iob-cache'
make: *** [Makefile:51: doc-build-all] Error 2

setup fails

in branch rewrite

iob_clk_en_rst_port.vs is replaced in some files but deleted before in others

generate pb and ug properly

use iob-uart as example

update readme

should explain what you can do with the repo. Not lecture people.

Understanding the flow of iob-cache

Hello Community
Is there any user documentation which explains basic flow of the "iob-cache" and how can we understand it.? I am getting perplexed with files getting generated after verilation in obj_dir directory. I am unable to generate user guide with the minimal commands provided.
It is getting difficult in understand as a user, how the back-end ,front-end sections are in sync with main memory section and can they be tested from testbench
Which sequence to follow for a basic successful test case

Thank you in advance.

Latest iob-cache does not compile due to warning being taken as error

/Work/ejas/iob-cache$ make sim SIMULATOR=verilator
make -C ./hardware/simulation/verilator run
make[1]: Entering directory '/home/tejas/Work/ejas/iob-cache/hardware/simulation/verilator'
verilator -Wno-WIDTH --trace --cc --exe -I../../../hardware/include -I../../../submodules/LIB/hardware/include -I../../../hardware/testbench ../../../submodules/MEM/hardware/regfile/iob_regfile_sp/iob_regfile_sp.v ../../../submodules/MEM/hardware/ram/iob_ram_2p/iob_ram_2p.v ../../../submodules/MEM/hardware/ram/iob_ram_2p_asym/iob_ram_2p_asym.v ../../../submodules/MEM/hardware/fifo/iob_fifo_sync/iob_fifo_sync.v ../../../submodules/MEM/hardware/ram/iob_ram_sp/iob_ram_sp.v ../../../hardware/src/back-end-native.v ../../../hardware/src/read-channel-native.v ../../../hardware/src/cache-control.v ../../../hardware/src/write-channel-native.v ../../../hardware/src/back-end-axi.v ../../../hardware/src/read-channel-axi.v ../../../hardware/src/onehot-to-bin-encoder.v ../../../hardware/src/write-channel-axi.v ../../../hardware/src/cache-memory.v ../../../hardware/src/front-end.v ../../../hardware/src/replacement-policy.v ../../../hardware/src/iob_cache.v ../../../hardware/src/iob-cache-axi.v testbench.cpp ../../../submodules/AXI/submodules/V_AXI/rtl/axi_ram.v --top-module iob_cache
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'arst'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_w_en'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_w_data'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_w_addr'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_r_en'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_r_addr'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Warning-PINMISSING: ../../../hardware/src/cache-memory.v:113: Cell has missing pin: 'ext_mem_r_data'
write_throught_buffer
^~~~~~~~~~~~~~~~~~~~~
%Error: Exiting due to 7 warning(s)
make[1]: *** [Makefile:12: run] Error 1
make[1]: Leaving directory '/home/tejas/Work/ejas/iob-cache/hardware/simulation/verilator'
make: *** [Makefile:18: sim] Error 2

Kindly guide to resolve the same.

Flow control on the user side?

rename sources

do note use '-'

add prefix iob_cache_

module name should match

test should pass in the end

make sim

CACHE_DIR:=.
include ./core.mk

sim:
make -C $(CACHE_SIM_DIR) all

Had to add an all in the Makefile, otherwise the make sim would output a string called CACHE

make test target is needed

cache should have an individual test and added to Jenkins

'x' data read from cache

I'm trying to connect iob_cache directly to a picorv32 core. But I noticed that, when reading from certain address, the rdata turns to be 'x'. It happens when the addr[3:0] == 4'b0000.

I create the iob_cache instance as follow:

iob_cache #(
  .N_WAYS(2),
  .LINE_OFF_W(7),
  .WORD_OFF_W(4),
  .WTBUF_DEPTH_W(5),
  .CTRL_CACHE(0),
  .CTRL_CNT(0)
) cache_inst (
  .clk(clk),
  .reset(!resetn),
  // Front-end interface
  .valid           ( pico_valid               ),
  .addr            ( pico_addr[31:2]          ),
  .wdata           ( pico_wdata               ),
  .wstrb           ( pico_wstrb               ),
  .rdata           ( pico_rdata               ),
  .ready           ( pico_ready               ),
  // Ctrl signals
  .force_inv_in    ( 1'b0                     ),
  .force_inv_out   ( /* not used */           ),
  .wtb_empty_in    ( 1'b1                     ),
  .wtb_empty_out   ( /* not used */           ),
  // Back-end interface
  .mem_valid       ( mem_valid                ),
  .mem_addr        ( mem_addr                 ),
  .mem_wdata       ( mem_wdata                ),
  .mem_wstrb       ( mem_wstrb                ),
  .mem_rdata       ( mem_rdata                ),
  .mem_ready       ( mem_ready                )
);

I wonder if there're some rules to follow when using iob_cache? The problem seems to have something to do with cache_memory module, but I'm not sure what exactly causes the x data.

BE_ADDR_W > FIRM_ADDR_W

gives a multi-source warning when integrated in iob-soc but works -- it would be nice to remove this warning

Do not close an open gtkwave automatically

I suggest not to close an open gtkwave automatically when running a new simulation.
There might be situations when parallel debug sessions are required (different VCD files, different rtl, etc.)

BACKEND WIDTH 64 and N_WAY 2 in WRITE_BACK mode ERROR

          Hi，I've fonud a testcase you mentioned above:

the iob-cache's parameter set is:

It's backend is 64 bit AXI interface and it is connected with a AXI-bus-matrix's master port.
A 64 bit memory with AXI interface is connected with AXI-bus-matrix's slave port.

if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

then no fail msg uart will put.

However, if the software is this:

*(volatile int *)(0xf0088000) = 0x2;
*(volatile int *)(0xf0090000) = 0x3;
*(volatile int *)(0xf0098000) = 0x4;
if (*(volatile int *)(0xf0088000) != 0x2)
  uart0_putline("0xf0088000 fail\n");

error will happen:

the waveform:

I think that the errors may because of these signals

EDIT: I found that if I set cache's N_WAYS to 1, there will be no error

Originally posted by @spzeno in #241 (comment)

Open gtkwave only if needed

I suggest to open gtkwave only if needed instead of opening it whenever a VCD file is generated.
I think that generating a VCD file might be required for other purposes in addition of visualizing waveforms immediately.

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