feifan1996 Goto Github PK

-

机器学习实战python代码

00_image_rotate

视频旋转（2019FPGA大赛）

8-bits-risc-cpu-verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（**处理器）简单结构和Verilog实现。

996.icu

Repo for counting stars and contributing. Press F to pay respect to glorious developers.

aham3soc

SoC Based on ARM Cortex-M3

ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

algorithm-prratice

algorithms

The codes and my solutions to exercises from the book "Algorithms" (4th edition) by Robert Sedgewick and Kevin Wayne.

answer-of-algorithm-introduction-english-

算法导论答案英文版

antenna-tests

Arduino code for antenna tests with 2x2 MIMO antenna with OFDM

arduino-vlc

This repository contains the code of my Deploma Theses which title is Visual Light Communications for Internet of Things applications

arduinovlc

Visible Light Communication using Arduino

arm-foss

Experiment in creating an ARM Cortex-M0 SoC using only open source tools. This was just moved here from https://bitbucket.org/vahidi/arm-foss/

arm_soc

automatic-verilog

automatic-verilog based on vimscript

awesome-dv

Awesome ASIC design verification

awesome-interview

Collection of awesome interview references.

barebonescortexm0

Extremely basic CortexM0 SoC based on ARM DesignStart Eval

basic_verilog

Must-have verilog systemverilog modules

chainsaw

chilipepper

Laboratory exercises and references designs for teaching wireless algorithm implementation in FPGAs.

cm3soc-demo

SoC Demo Based on Cortex-M3 Softcore Processor

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cores-swerv

SweRV EH1 core

cores-swerv-eh2

cortexm0_soc

Cortex M0 based SoC

cortexm0_soc_task

Step by step tutorial for building CortexM0 SoC

cplusplusthings

C++那些事

cvxquad

Implementation in MATLAB-based CVX of a new approximation strategy to support exponential cone using symmetric cone solvers and various other functions derived from matrix logarithm

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!