feifan1996 Goto Github PK

design-and-verification-of-ldpc-decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.

detecthumanfaces

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

digital-communications-zynq-

e200_opensource

The Ultra-Low Power RISC Core

fpga

FPGA

hand-writing-digital-recognization-based-on-fpga

Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.

i2c_vip

Verification IP for I2C protocol

iob-cache

Verilog configurable cache

ldpc-decoder

Implementation of Partially Parellel LDPC Code Decoder in Verilog

linux-lab

Docker/Qemu Based Linux Kernel Learning, Development and Testing Environment

logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

machine

machine-learning

zhihua zhous;s book

machine-learning-1

:zap:机器学习实战（Python3）：kNN、决策树、贝叶斯、逻辑回归、SVM、线性回归、树回归

machinelearninginaction

Source Code for the book: Machine Learning in Action published by Manning

math

SpinalHDL Hardware Math Library

open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

opentitan

OpenTitan: Open source silicon root of trust

openwifi

open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

pcc

Resources for Python Crash Course, from No Starch Press.

polar

C and MATLAB implementation for Polar encoding and decoding

polar-3gpp-matlab

Matlab simulations of the encoder and SCL decoder for the New Radio polar code from 3GPP Release 15

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

pynq_softmax

achieve softmax in PYNQ with heterogeneous computing.

pyuvm

The UVM written in Python

raptor

Arm Cortex-M0 based Customizable SoC for IoT Applications

riscsoc

RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

sdr_matlab_ofdm_802.11a

:satellite: Using Software Designed Radio to transmit OFDM QPSK signals at 5 GHz

shadowsocks-windows

If you want to keep a secret, you must also hide it from yourself.