ultraembedded / core_uriscv Goto Github PK

type_load_w and type_store_w signals on riscv_core.v should be defined before being used

AFAIK this is not standard SystemVerilog, did not tried with iverilog but this is failing both with SNPS dc and Cadence's genus

Hi,

When I try to build with the provided Makefile in tb/tb_core_icarus I get the following error

iverilog -o build//output.out ../../src_v/riscv_core.v ../../src_v/uriscv_alu.v ../../src_v/uriscv_branch.v ../../src_v/uriscv_csr.v ../../src_v/uriscv_defs.v ../../src_v/uriscv_lsu.v ../../src_v/uriscv_muldiv.v ./tb_top.v ./tcm_mem.v ./tcm_mem_ram.v -I../../src_v -I. -DTRACE=1 -Dverilog_sim
../../src_v/riscv_core.v:102: Include file uriscv_defs.v not found
../../src_v/riscv_core.v:101: syntax error
I give up.
make: *** [build//output.out] Error 2

All is good if I change the order of VFLAGS on the command line in the Makefile. So

iverilog -o $@ $(SRC_V) $(VFLAGS)

becomes

iverilog $(VFLAGS) -o $@ $(SRC_V)

I don't know what the real issue is but the fix works for me!

Cheers,
Derek