dpretet Goto Github PK

ascend-freepdk45

A free standard cell library for SDDS-NCL circuits

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

autofpga

A utility for Composing FPGA designs from Peripherals

axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

binary-tree

A python implementation of binary tree

blog

The Critical Path - a rambly FPGA blog

bottlejquery

An example found on the web to communicate between a Bottle server and a web page using JQuery

bster

Implementation of a binary search tree algorithm in a FPGA/ASIC IP

cdc

Repository gathering basic modules for CDC purpose

chacha20

Chacha20 Implementation in SystemVerilog for FPGA and ASIC

chacha20.c

Basic implementation of Chacha2 algorithm in C

dark-tech

dotfiles

Zsh, Neovim & Tmux dotfiles

etherumfromscratch

Etherum introduction

fpga_as_a_service

friscv

RISCV CPU implementation in SystemVerilog

hdlparse

Simple parser for extracting VHDL documentation

hw

RTL, Cmodel, and testbench for NVDLA

linuxinstall

An JSON storing all packages to install to configure my Linux setup

machine_learning_basics

Plain python implementations of basic machine learning algorithms

meduram

Multi-port BRAM IP for ASIC and FPGA

ml.stanford

My programing execrcises for Andrew Ng Machine Learning Course

ml.washington

Machine Learning course from Washington University

neovim

Vim-fork focused on extensibility and usability

nng

nanomsg-next-generation -- light-weight brokerless messaging

nvim-lspconfig

Quickstart configurations for the Nvim LSP client

opensocfabric

OpenSoC Fabric - A Network-On-Chip Generator

pool_arena.c

Pool arena implementation

qlmarkdown

QuickLook generator for Markdown files.

restful-caller