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advanced-physical-design-using-openlane-and-skywater-130-pdk

This repository contains a step by step procedure to the complete RTL2GDSII flow of PICORV32A RISC-V core design using open-source EDA tool OpenLANE and Google-Skywater’s first manufacturable open source 130nm PDK.

advanced-physical-design-using-openlane-sky130

This repository contains the details of steps followed and summary of hands on done on doing the Advanced Physical Design Using OpenLANE/SKY130 workshop. The workshop focuses on complete ASIC Design flow from RTL2GDS using Open Source EDA tool OpenLANE and Google SKYWater130nm pdk. The core of design PICORV32A used is of RISC-V architechture.

advanced_physical_design-using-openlane_sky130

This repository contains all the information studied and created during the Advanced Physical Design Using OpenLANE / SKY130 workshop. It is primarily focused on a complete RTL2GDS flow using the open-source flow named OpenLANE. PICORV32A RISC-V core design is used for the purpose.

apd-openlane-skywater130-workshop

This Repository mainly created to focus on the work-done in 5 Days workshop of Adavance Physical Design using OpenLANE/SkyWater130. The Workshop mainly focus on to hands on experience of the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

awesome-riscv-cores

A curated list of spec, maturity comparison between current Open RISC-V cores.

axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

biriscv

32-bit Superscalar RISC-V CPU

canary-rv32ima

Hardware Scheduled Dual Core RISC-V (OOO IMAC + Pipelined IA) Processor with a snoop bus interconnect (MESI Protocol) -- all in SystemVerilog

cellrv32

:milky_way: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

clusterv-soc

Quad cluster of RISC-V cores with peripherals and local memory

cnrv-fpu

Basic floating-point components for RISC-V processors

complete-pipelined-risc-v-cpu-core-

core-v-cores

CORE-V Family of RISC-V Cores

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

core-v-xif

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

core_uriscv

Another tiny RISC-V implementation

cores-swerv-support-package

Processor support packages

cores-veer-eh1

VeeR EH1 core

cores-veer-eh2

CHIPSALLIANCE Cores-VeeR-EH2

cores-veer-el2

VeeR EL2 Core

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

cva5

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

cva5-accelerators

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-softcore-contest

National French competition for optimizing the power consumption of an Application class 6-stage RISC-V CPU (CORE-V CVA6)

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!