Topic: logic-synthesis Goto Github
Some thing interesting about logic-synthesis
Some thing interesting about logic-synthesis
logic-synthesis,MATLAB and HDL models of ACA-CSU approximate adders
User: alishkanani
logic-synthesis,A collection of digital logic circuits
User: anthonyabeo
logic-synthesis,Automated conversion from CHP to PRS using syntax-directed translation
Organization: asyncvlsi
logic-synthesis, To generate an electrical circuit from the given input and output boolean values.
User: atul-khobragade
logic-synthesis,This is a tutorial on standard digital design flow
User: bojackchen
logic-synthesis,Fast Heuristic Minimization of Exclusive-Sums-of-Products
User: boschmitt
logic-synthesis, Logic synthesis and verification framework
User: boschmitt
logic-synthesis,An open-source design automation framework for Field-coupled Nanotechnologies
Organization: cda-tum
Home Page: https://fiction.readthedocs.io
logic-synthesis,Mirror of espresso, a two-level logic synthesis tool
User: changmg
Home Page: http://www.ecs.umass.edu/ece/labs/vlsicad/ece667/links/espresso.html
logic-synthesis,Efficient resubstitution-based approximate logic synthesis
User: changmg
logic-synthesis,Awesome machine learning for logic synthesis
User: chenghao-yang
logic-synthesis,
User: clin99
logic-synthesis,Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Organization: cornell-zhang
logic-synthesis,Functionally Reduced And-Inverter Graph
User: daikon-sun
logic-synthesis,C++ header-only And-Inverter graph (AIG) library
User: hriener
logic-synthesis,C++ header-only ESOP library
User: hriener
logic-synthesis,C++ parsing library for simple formats used in logic synthesis and formal verification
User: hriener
logic-synthesis,DATC RDF
Organization: ieee-ceda-datc
logic-synthesis,Coursework of NTHU CS613200 Advanced Logic Synthesis
User: koyama-tsubasa
logic-synthesis,IDEA project source files
Organization: lnis-uofu
logic-synthesis,Showcase examples for EPFL logic synthesis libraries
Organization: lsils
logic-synthesis, Approximate Logic Synthesis and Bi-Decomposition of Sum Of Products forms
User: marcocosta97
logic-synthesis,A circuit toolkit
User: msoeken
logic-synthesis,C++ truth table library
User: msoeken
logic-synthesis,A logic synthesis tool
User: nbulsi
logic-synthesis,An application using Cadence IC Package
User: nikolaosgian
logic-synthesis,A collection of the Logic Synthesis about peoples/papers/projects/tutorials...
User: nlwmode
logic-synthesis,A circuit folding interface in ABC system
Organization: ntu-alcomlab
Home Page: https://po-chun-chien.github.io/publication/2020-06-thesis
logic-synthesis,Code repository for the IWLS 2021 Programming Contest
Organization: ntu-alcomlab
Home Page: https://www.iwls.org/iwls2021/
logic-synthesis,This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.
Organization: nyu-mlda
Home Page: https://openreview.net/forum?id=0t1O8ziRZp
logic-synthesis,ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning
Organization: nyu-mlda
logic-synthesis,OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.
Organization: nyu-mlda
logic-synthesis,A Logic Synthesis tool based on "Mockturtle: EPFL Logic Synthesis Library " and "ABC: System for Sequential Logic Synthesis and Formal Verification""
User: panhomyoung
logic-synthesis,An implementation of binary decision tree with fringe-features extraction.
User: po-chun-chien
Home Page: https://po-chun-chien.github.io/projects/5.ML+LS/
logic-synthesis,An implementation of LUT-Net learning procedure
User: po-chun-chien
Home Page: https://po-chun-chien.github.io/projects/5.ML+LS/
logic-synthesis,Electronic design automation for Minecraft
User: porglezomp
logic-synthesis,Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
User: porglezomp
logic-synthesis,This article describes how embedded languages and recursion can be used to create a tool that synthesizes a relatively efficient logical circuit for any chosen permutation of the set of all bit vectors of some fixed length.
Organization: reity
logic-synthesis,ABACUS is a tool for approximate logic synthesis
Organization: scale-lab
logic-synthesis,Benchmarks for Approximate Circuit Synthesis
Organization: scale-lab
logic-synthesis,An Approximate Logic Synthesis Framework based on Boolean Matrix Factorization
Organization: scale-lab
logic-synthesis,DRiLLS: Deep Reinforcement Learning for Logic Synthesis Optimization (ASPDAC'20)
Organization: scale-lab
logic-synthesis,The Verilog source code for DRUM approximate multiplier.
Organization: scale-lab
logic-synthesis,EDA physical synthesis optimization kit
Organization: scale-lab
Home Page: https://woset-workshop.github.io/PDFs/2020/a09.pdf
logic-synthesis,Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction
User: shobro
logic-synthesis,Highly efficient delay-driven approximate logic synthesis
Organization: sjtu-ectl
logic-synthesis,An approximate logic synthesis tool under the maximum error constraint
Organization: sjtu-ectl
logic-synthesis,VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
Organization: sjtu-ectl
logic-synthesis,A boolean matcher that computes the NPN canonical representative for a given boolean function.
User: snowkylin
logic-synthesis,Toolset to capture, simulate, synthesize and verify graph models
Organization: workcraft
Home Page: https://workcraft.org
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