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Hi there 👋

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  • 🔭 I’m currently working at PCL
  • 🌱 I’m currently learning EDA Logical Synthesis
  • 👯 I’m looking to collaborate on traditional logical synthesis algorithms.
  • 💬 Ask me about software engineering/compiler/EDA/Robot SLAM, etc.
  • 📫 How to reach me: nlwmode At gmail Dot com

nlwmode's Projects

3d_navigation icon 3d_navigation

Global and local path planner plugins for ROS move_base which move the robot in 2D (x,y,angle) but avoid collisions using full 3D data (robot meshes and environment octomap).

aiger icon aiger

AIGER And-Inverter-Graph Library

circuit-parser icon circuit-parser

C++ parsing library for simple formats used in logic synthesis and formal verification

cpp_interview_guide icon cpp_interview_guide

C++开发相关面试题目:涉及C++面试常问题、设计模式、数据结构、操作系统及网络等。完善中...

cudd icon cudd

CUDD stands for Colorado University Decision Diagram. It is a package for the manipulation of Binary Decision Diagrams (BDDs), Algebraic Decision Diagrams (ADDs) and Zero-suppressed Binary Decision Diagrams (ZDDs).

ifpga-mapper icon ifpga-mapper

iFPGA mapper for technology mapping in logic synthesis.

leetcodeanimation icon leetcodeanimation

Demonstrate all the questions on LeetCode in the form of animation.(用动画的形式呈现解LeetCode题目的思路)

mec icon mec

Mapping Equivalence Checking

ndt_omp icon ndt_omp

Multi-threaded and SSE friendly NDT algorithm

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