I have managed to build the simulation via:
make CONFIG=DebugConfig in vsim directory
next I would like launch the RTL simulation and but the debug tool couldnt connect correctly when I run:
./DebugConfig-sim +waitdebug
of which I didnt manage to see the output on the terminal. Basically there is nothing printed at all.
Glip TCP DPI listening on port 23000 and 23001

I have successfully build both Glip Software and Open SoC Debug software
and also I tried to connect the daemon on the second terminal
opensocdebugd tcp
I observed the following outcome:

Open SoC Debug Daemon
Backend: tcp
glip: glip_open: Cannot open backend
glip: glip_write_b: No connection; you need to call glip_open() first!
glip: glip_read_b: No connection; you need to call glip_open() first!
opensocdebugd: ../../src/connection-standalone.c:67: receiver_thread_function: Assertion `rv == 0' failed.
Aborted (core dumped)

any advice what could have possibly gone wrong?

Hi, guys:

From the riscv-privileged-v1.10, chapter 4.1.12, I find that the "Supervisor Address Translation and Protection (satp)" register contains a Mode and ASID and PPN。

Also, from the code in https://github.com/riscv/riscv-linux/blob/riscv-next/arch/riscv/kernel/head.S, there are some codes to configure the sptbr register using the SPTBR_MODE.

/* Compute sptbr for kernel page tables, but don't load it yet */
	la a2, swapper_pg_dir
	srl a2, a2, PAGE_SHIFT
	li a1, SPTBR_MODE
	or a2, a2, a1

	/* Load trampoline page directory, which will cause us to trap to
	   stvec if VA != PA, or simply fall through if VA == PA */
	la a0, trampoline_pg_dir
	srl a0, a0, PAGE_SHIFT
	or a0, a0, a1
	sfence.vma
	csrw sptbr, a0

However, in the lowrisc's version linux(https://github.com/lowRISC/riscv-linux), the head.S does not contain codes to configure the sptbr...And I don't see any codes in the linux to set the Modes of sptbr too...

So I am just wondering how lowrisc handle the Mode filed in the sptbr(satp).

Any responses are welcomed! Thanks!

Hi when I tried to
make
for /lowrisc-chip/vcs
I get the following errors:

Error-[IND] Identifier not declared .../lowrisc-chip/minion_subsystem/verilog/minion_soc.sv, 66 Identifier 'one_hot_rdata' has not been declared yet. If this error is not expected, please check if you have set default_nettype to none.`

any advice?

TODO list:

• clean up a branch
• set up the initial lowrisc-chip chisel top for make
• make our own Node to allow attaching parameters (virtual slaves) but without connect bundles.
• reimplement trait HasMasterAXI4MMIOPort to allow configuration time expansion of multiple slaves to the AXI4SlaveParameters.
• figure out how to add device tree information.
• support interrupt lines for virtual slaves
• bump riscv-tools
• rewrite the SV tope-level
• modify bootrom
• temporarily mute run-control debugger by using a dummy SimDTM
• pass isa regression
• revise the bare-metal tests
• test for interrupts
• find out how to utilize the run-control debugger

Notes:

• Directly attaching virtual peripherals to a AXI master port is a dead end. The AXI parameter is lack of the capability to describe multiple devices! Only TileLink parameters are fully fledged.

Hello.

I have successfully booted Linux on my FPGA.

After booting, there is no compiler in the root file system.
So, I want to put the compiler in the root filesystem.
When I added the compiler to the root file system, the size of the image file was 188 Mbytes.
(Original size : 4Mbyte)
Is it possible to boot this size too?

In a potential corner case, I observed that L1 cache might drop a write:
Suppose we have MESI between L1 and L2, and a specific cache block in core 0 is in ExclusiveClean state. Then, a write to this cache block and a invalidateData probe of this cache block from other core come to the L1 cache simultaneously. What is happening is shown below as a timeline:

EDIT: After re-looking at the waveform, I think this is the correct timeline

cpu_req write arrives --> probe_req arrives --> probe_req read meta (E-clean state) --> cpu_req allocate MSHR since E-clean needs to be changed into E-Dirty --> MSHR change meta from E-Clean to E-Dirty --> MSHR replay the instr and and read the new meta (E-Dirty) --> probeUnit change meta from E-Dirty to Invalid and send releaseAck --> the cpu_req write commits the write to data array to stage 3

So generally the problem happens because the read&write of meta has some gap in between, and seems to me there are no mechanism in between to prevent dual modification

Since I am not fully confident with my observation here, I'd appreciate if someone can help me check if the last step will indeed happen as described here in the current Rocket nbdcache design.

Hello,
I'm trying to add simple DMA device to the lowrisc (lowRISC 0-4 milestone release), I'm following the tutorial on the following link:
http://www.lowrisc.org/docs/internship-2016/device-tutorial/

But it seems the code there is not compatible with the latest release and the compilation fails, could you please help with the syntax or code that adds DMA device that is working with the latest release?

Errors are:.
.
.
.

[error] (lowrisc_chip/compile:run) Nonzero exit code: 1
[error] Total time: 15 s, completed Aug 23, 2017 1:42:11 PM
/home/ssau/lowrisc-chip/Makefrag-build:9: recipe for target '/home/ssau/lowrisc-chip/vsim/generated-src/Top.DefaultL2Config.sv' failed
make: *** [/home/ssau/lowrisc-chip/vsim/generated-src/Top.DefaultL2Config.sv] Error 1

Would it be possible to change the bus width size of NastiIO fron 64 bits to 128bits? That would apply to nasti.r.bits.data and nasti.w.bits.data specifically. The purpose is being to perform read and write to DDR in 128bits instead of 64.
Any advice?

Hello,

Is it possible to push another small rtos with rocket cores to the fpga instead of riscv-linux ? The rtos in question has its own gcc.
Can an RTOS be ported on top of the BBL for the untethered (or tethered (ucb-bar)) systems ?
If so, could you please explain what would be a good place to start ?

Thank you

Hello,

Is it possible to do an FPGA demo in a zynq ?
I got this error when generating a bitstream for the default fpga kc705:

source script/make_project.tcl
# set mem_data_width {128}
# set axi_id_width {9}
# set origin_dir "."
# set base_dir "../../.."
# set common_dir "../../common"
# set project_name [lindex $argv 0]
# set CONFIG [lindex $argv 1]
# set orig_proj_dir [file normalize $origin_dir/$project_name]
# create_project $project_name $origin_dir/$project_name
# set proj_dir [get_property directory [current_project]]
# set obj [get_projects $project_name]
# set_property "default_lib" "xil_defaultlib" $obj
# set_property "board_part" "xilinx.com:kc705:part0:1.1" $obj
ERROR: [Board 49-71] The board_part definition was not found for xilinx.com:kc705:part0:1.1. The project's board_part property was not set, but the project's part property was set to xc7k70tfbv676-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
INFO: [Common 17-206] Exiting Vivado at Wed May  3 15:37:10 2017...
make: *** [lowrisc-chip-imp/lowrisc-chip-imp.xpr] Error 1

And then,

Vivado% get_board_parts
em.avnet.com:zed:part0:0.9 em.avnet.com:zed:part0:1.0 em.avnet.com:zed:part0:1.1 em.avnet.com:zed:part0:1.2 em.avnet.com:zed:part0:1.3 xilinx.com:ac701:part0:1.0 xilinx.com:ac701:part0:1.1 xilinx.com:ac701:part0:1.2 xilinx.com:zc702:part0:0.9 xilinx.com:zc702:part0:1.0 xilinx.com:zc702:part0:1.1 xilinx.com:zc702:part0:1.2

Is there something I can do to generate bitsream in a zedboard ?

Thank you !

I have two questions when looking at the rocket code:

I noticed that L1 cache in rocket core has something called "replay", but I am not sure what this is for. Could anyone share some info about it?

Also, I noticed that the L2HellaCache has some atomic operation support (including an AMOALU each bank). But I am wondering in what case will L2 be handling AMOs instead of core L1s handling by themselves.

Thanks!

Hello,

when trying to run make sim in ~lowrisc-chip/vsim (untether-v2.0), I get the following error:

alpha@alpha-VirtualBox:~/lowrisc-chip/vsim$ make sim
cd verilator && make -f Vchip_top.mk
/bin/bash: line 0: cd: verilator: No such file or directory
make: *** [DefaultConfig-sim] Error 1

My environment variables are:

alpha@alpha-VirtualBox:~/lowrisc-chip/vsim$ which verilator
/usr/bin/verilator

Can anyone please tell why this isn't working ?

Thank you !

Hi I am evaluating various RISCV Cores. I am getting the following results for Lowrisc V.4.0.

Is these results are correct or not? Can you share these information to me.

Can you update Dhrystone performance for Rocket Core?

I want to change the cache memory size for LowRISC. So can you share how to change the cache memory for LowRISC?

From the diagram in http://www.lowrisc.org/docs/tagged-memory-v0.1/rocket-core/, it seems to me this pipeline might not hit a high frequency target. For example, the dmem.req.addr is directly wired from the output of the ALU and to DCache. In the DCache pipeline, the addr input is fed into a mux and then directly to SRAM (data/meta).

I thought generally in order to achieve high frequency (say, @ 1GHz), one need to squeeze a single cycle to hold address steady for reading the SRAM due to the physical constraints. If the meta and data have input addr flopped and then output the read result using some combination logic, the output path that is going through the associative search and reach s2 flops will create a timing problem. On the other hand, if the meta and data have output data flopped, then the addr hold time before the clk edge might not be long enough with such long combinational chain before the SRAM.

Though the DCache diagram depicts the meta and data as a "flop", I assume it is just to demonstrate the timing behavior will be the same as other flops between stage 1 and 2, while essentially they are still standard SRAM or blockRAM and require a full cycle dedicated for read/write without other combinational logic. Please correct me if my understanding of the pipeline is wrong, thanks.

Hello,

I tested the v2 branch previously for my project. It is documented well on the lowrisc.org. I ported the design back to ZedBoard, making it use the half of ARM's DDR memory, and I provided the UART and SD card via PMODs. I followed the steps as described: built the boot.c, and ./bbl, provided the Linux kernel. Everything works.

I want to try the v3 branch as well. It interests me as it has a different boot mechanism than BBL, and on my project I need to work with a custom bootloader. (I am also trying to follow the Coreboot port progress) However, I didn't understand how to use the bootloader in this branch. It has an own sub-repository; however no description/readme.

Can you please, briefly explain how to use the bootloader of the v3 branch to boot Linux?

Kind Regards,

Hello,

I have enabled the debug on the Configs.Scala (case UseDebug => true ) and tried to generate verilog using : cd $TOP/vsim ; make verilog , the following compilation errors occurs, could you please help figure out what is the issue:

[jawad@localhost vsim]$ make verilog
cd /home/jawad/lowrisc-chip && mkdir -p /home/jawad/lowrisc-chip/vsim/generated-src && java -Xmx2048M -Xss8M -XX:MaxPermSize=256M -jar sbt-launch.jar "run Top DefaultL2Config --W0W --minimumCompatibility 3.0.0 --backend lowrisc_chip.LowRISCBackend --configName DefaultL2Config --compileInitializationUnoptimized --targetDir /home/jawad/lowrisc-chip/vsim/generated-src --configDump --noInlineMem"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] Loading project definition from /home/jawad/lowrisc-chip/project
[info] Set current project to lowrisc_chip (in build file:/home/jawad/lowrisc-chip/)
[info] Compiling 1 Scala source to /home/jawad/lowrisc-chip/target/scala-2.11/classes...
[info] Running lowrisc_chip.Run Top DefaultL2Config --W0W --minimumCompatibility 3.0.0 --backend lowrisc_chip.LowRISCBackend --configName DefaultL2Config --compileInitializationUnoptimized --targetDir /home/jawad/lowrisc-chip/vsim/generated-src --configDump --noInlineMem
Generated Address Map
io:ext:host 4000 - 403f
mem 40000000 - bfffffff
io:int:prci0 3000 - 3fff
io:int:rtc 2000 - 2fff
io:int:bootrom 0 - 1fff
Generated Configuration String
platform {
vendor lowRISC;
arch rocket;
};
rtc {
addr 0x2000;
};
ram {
0 {
addr 0x40000000;
size 0x80000000;
};
};
core {
0 {
0 {
isa rv64imafd;
timecmp 0x2008;
ipi 0x3000;
};
};
};

[error] (run-main-0) java.lang.reflect.InvocationTargetException
java.lang.reflect.InvocationTargetException
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:322)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:319)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at Chisel.Driver$$anonfun$executeUnwrapped$2.apply(Driver.scala:102)
at Chisel.Driver$$anonfun$executeUnwrapped$2.apply(Driver.scala:102)
at Chisel.Driver$.execute(Driver.scala:107)
at Chisel.Driver$.executeUnwrapped(Driver.scala:102)
at Chisel.Driver$.apply(Driver.scala:41)
at Chisel.chiselMain$.run(hcl.scala:67)
at lowrisc_chip.Run$.delayedEndpoint$lowrisc_chip$Run$1(LowRISCChip.scala:325)
at lowrisc_chip.Run$delayedInit$body.apply(LowRISCChip.scala:303)
at scala.Function0$class.apply$mcV$sp(Function0.scala:34)
at scala.runtime.AbstractFunction0.apply$mcV$sp(AbstractFunction0.scala:12)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.App$$anonfun$main$1.apply(App.scala:76)
at scala.collection.immutable.List.foreach(List.scala:381)
at scala.collection.generic.TraversableForwarder$class.foreach(TraversableForwarder.scala:35)
at scala.App$class.main(App.scala:76)
at lowrisc_chip.Run$.main(LowRISCChip.scala:303)
at lowrisc_chip.Run.main(LowRISCChip.scala)
at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:62)
at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.lang.reflect.Method.invoke(Method.java:498)
at sbt.Run.invokeMain(Run.scala:67)
at sbt.Run.run0(Run.scala:61)
at sbt.Run.sbt$Run$$execute$1(Run.scala:51)
at sbt.Run$$anonfun$run$1.apply$mcV$sp(Run.scala:55)
at sbt.Run$$anonfun$run$1.apply(Run.scala:55)
at sbt.Run$$anonfun$run$1.apply(Run.scala:55)
at sbt.Logger$$anon$4.apply(Logger.scala:85)
at sbt.TrapExit$App.run(TrapExit.scala:248)
at java.lang.Thread.run(Thread.java:748)
Caused by: cde.ParameterUndefinedException: Parameter DebugCtmScorBoardSize undefined.
at cde.World$TopLookup$1.apply(Parameters.scala:154)
at cde.World$_View.sym(Parameters.scala:110)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:295)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:290)
at cde.Parameters$KidLookup$1.apply(Parameters.scala:332)
at cde.World$_View.sym(Parameters.scala:110)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:295)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:290)
at cde.Parameters$KidLookup$1.apply(Parameters.scala:332)
at cde.Parameters.apply(Parameters.scala:317)
at open_soc_debug.HasDebugModuleParameters$class.$init$(debug_module.scala:39)
at open_soc_debug.DebugModuleModule.(debug_module.scala:55)
at open_soc_debug.RocketCoreTracer.(ctm.scala:112)
at rocket.Rocket$$anonfun$52.apply(rocket.scala:742)
at rocket.Rocket$$anonfun$52.apply(rocket.scala:742)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at rocket.Rocket.(rocket.scala:742)
at rocket.RocketTile$$anonfun$7.apply(tile.scala:44)
at rocket.RocketTile$$anonfun$7.apply(tile.scala:44)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at rocket.RocketTile.(tile.scala:44)
at lowrisc_chip.Top$$anonfun$21$$anonfun$apply$5.apply(LowRISCChip.scala:131)
at lowrisc_chip.Top$$anonfun$21$$anonfun$apply$5.apply(LowRISCChip.scala:131)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at lowrisc_chip.Top$$anonfun$21.apply(LowRISCChip.scala:131)
at lowrisc_chip.Top$$anonfun$21.apply(LowRISCChip.scala:131)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.immutable.Range.foreach(Range.scala:166)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.AbstractTraversable.map(Traversable.scala:104)
at lowrisc_chip.Top.(LowRISCChip.scala:131)
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:322)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:319)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at Chisel.Driver$$anonfun$executeUnwrapped$2.apply(Driver.scala:102)
at Chisel.Driver$$anonfun$executeUnwrapped$2.apply(Driver.scala:102)
at Chisel.Driver$.execute(Driver.scala:107)
at Chisel.Driver$.executeUnwrapped(Driver.scala:102)
Caused by: scala.MatchError: DebugCtmScorBoardSize (of class open_soc_debug.DebugCtmScorBoardSize$)
at lowrisc_chip.BaseConfig$$anonfun$1.apply(Configs.scala:125)
at lowrisc_chip.BaseConfig$$anonfun$1.apply(Configs.scala:22)
at cde.Config$$anonfun$addDefinitions$1.apply(Config.scala:23)
at cde.Config$$anonfun$addDefinitions$1.apply(Config.scala:22)
at cde.Config$$anonfun$addDefinitions$1.apply(Config.scala:23)
at cde.Config$$anonfun$addDefinitions$1.apply(Config.scala:22)
at cde.World$TopLookup$1.apply(Parameters.scala:152)
at cde.World$_View.sym(Parameters.scala:110)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:295)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:290)
at cde.Parameters$KidLookup$1.apply(Parameters.scala:332)
at cde.World$_View.sym(Parameters.scala:110)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:295)
at cde.Parameters$$anonfun$makeMask$3.apply(Parameters.scala:290)
at cde.Parameters$KidLookup$1.apply(Parameters.scala:332)
at cde.Parameters.apply(Parameters.scala:317)
at open_soc_debug.HasDebugModuleParameters$class.$init$(debug_module.scala:39)
at open_soc_debug.DebugModuleModule.(debug_module.scala:55)
at open_soc_debug.RocketCoreTracer.(ctm.scala:112)
at rocket.Rocket$$anonfun$52.apply(rocket.scala:742)
at rocket.Rocket$$anonfun$52.apply(rocket.scala:742)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at rocket.Rocket.(rocket.scala:742)
at rocket.RocketTile$$anonfun$7.apply(tile.scala:44)
at rocket.RocketTile$$anonfun$7.apply(tile.scala:44)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at rocket.RocketTile.(tile.scala:44)
at lowrisc_chip.Top$$anonfun$21$$anonfun$apply$5.apply(LowRISCChip.scala:131)
at lowrisc_chip.Top$$anonfun$21$$anonfun$apply$5.apply(LowRISCChip.scala:131)
at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
at Chisel.Module$.apply(Module.scala:50)
at lowrisc_chip.Top$$anonfun$21.apply(LowRISCChip.scala:131)
at lowrisc_chip.Top$$anonfun$21.apply(LowRISCChip.scala:131)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.immutable.Range.foreach(Range.scala:166)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.AbstractTraversable.map(Traversable.scala:104)
at lowrisc_chip.Top.(LowRISCChip.scala:131)
at sun.reflect.NativeConstructorAccessorImpl.newInstance0(Native Method)
at sun.reflect.NativeConstructorAccessorImpl.newInstance(NativeConstructorAccessorImpl.java:62)
at sun.reflect.DelegatingConstructorAccessorImpl.newInstance(DelegatingConstructorAccessorImpl.java:45)
at java.lang.reflect.Constructor.newInstance(Constructor.java:423)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:322)
at lowrisc_chip.Run$$anonfun$40.apply(LowRISCChip.scala:319)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
at Chisel.Driver$$anon$$$$215427f2c411fef219772bc14f46c4$$$$nfun$apply$1.apply(Driver.scala:102)
java.lang.RuntimeException: Nonzero exit code: 1
at scala.sys.package$.error(package.scala:27)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:1943)
at sbt.BuildCommon$$anonfun$toError$1.apply(Defaults.scala:1943)
at scala.Option.foreach(Option.scala:236)
at sbt.BuildCommon$class.toError(Defaults.scala:1943)
at sbt.Defaults$.toError(Defaults.scala:38)
at sbt.Defaults$$anonfun$runTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:719)
at sbt.Defaults$$anonfun$runTask$1$$anonfun$apply$36$$anonfun$apply$37.apply(Defaults.scala:717)
at scala.Function1$$anonfun$compose$1.apply(Function1.scala:47)
at sbt.$tilde$greater$$anonfun$$u2219$1.apply(TypeFunctions.scala:40)
at sbt.std.Transform$$anon$4.work(System.scala:63)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:226)
at sbt.Execute$$anonfun$submit$1$$anonfun$apply$1.apply(Execute.scala:226)
at sbt.ErrorHandling$.wideConvert(ErrorHandling.scala:17)
at sbt.Execute.work(Execute.scala:235)
at sbt.Execute$$anonfun$submit$1.apply(Execute.scala:226)
at sbt.Execute$$anonfun$submit$1.apply(Execute.scala:226)
at sbt.ConcurrentRestrictions$$anon$4$$anonfun$1.apply(ConcurrentRestrictions.scala:159)
at sbt.CompletionService$$anon$2.call(CompletionService.scala:28)
at java.util.concurrent.FutureTask.run(FutureTask.java:266)
at java.util.concurrent.Executors$RunnableAdapter.call(Executors.java:511)
at java.util.concurrent.FutureTask.run(FutureTask.java:266)
at java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1142)
at java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:617)
at java.lang.Thread.run(Thread.java:748)
[error] (lowrisc_chip/compile:run) Nonzero exit code: 1
[error] Total time: 8 s, completed Aug 24, 2017 12:05:53 PM
/home/jawad/lowrisc-chip/Makefrag-build:9: recipe for target '/home/jawad/lowrisc-chip/vsim/generated-src/Top.DefaultL2Config.sv' failed
make: *** [/home/jawad/lowrisc-chip/vsim/generated-src/Top.DefaultL2Config.sv] Error 1

I've been trying to get a build environment set up for fpga testing. I've tried meticulously to follow the info here and on lowrisc.org/docs but have hit a wall.

I'm trying to run the riscv-tools/make_root.sh script to create a root.bin. It sets a variable for the intended fpga board eg. nexys_ddr. It tries to build bbl for the fpga bootloader but dev_map.h is missing. I've searched everywhere and this file appears to not exist.

build bbl...
configure: WARNING: using cross tools not prefixed with host triplet
In file included from ../machine/mtrap.h:4:0,
                 from ../bbl/bbl.c:2:
../machine/encoding.h:6:21: fatal error: dev_map.h: No such file or directory
 #include "dev_map.h"
                     ^
compilation terminated.
In file included from ../machine/mtrap.h:4:0,
                 from ../bbl/kernel_elf.c:3:
../machine/encoding.h:6:21: fatal error: dev_map.h: No such file or directory
 #include "dev_map.h"
                     ^
compilation terminated.
make: *** [bbl.o] Error 1
make: *** Waiting for unfinished jobs....
make: *** [kernel_elf.o] Error 1

I tried just commenting it out but it actually appears to need the value

#define DRAM_BASE          DEV_MAP__mem__BASE

For several places in that build.

I'm building linux-4.6.2 and busybox-1.2.1. It appears everything is as current as available.

Either I've missed a step somewhere, or some code is missing, or the current docs aren't complete in how to build everything. I'd appreciate any suggestions. It does seem to me that there ought to be a dev_map.h included with the board specific files but none is present for me.

Thx.

I suggest we should trim the useless branches after the minion-v0.4 release.
If some branches are useful but isolated, such the branches for previous releases, of course they remain untouched.
However, for the branches that used to be working attempts and have then being merged into release branches or main branch, they should be removed.
I am thinking of branches like tagpipe, tagpipe-new-toolchain, tagpipe-minion-merge, minion-system, minion-sd, eth_debug.

It would be awesome to have the system id which is provided by the SCM be the first bytes of the current git commit hash. I think we can do something with either the Makefiles or tcl-pre for synthesis.

I see the riscv-linux/arch/riscv/ in lowrisc is older then riscv github(https://github.com/riscv/riscv-linux/tree/riscv-next/arch/riscv), so I am wondering when lowrisc will merge the latest linux and support SMP well. thanks.

@jrrk

Hi. I have been here a long time.

I want to know the Linux boot procedure of LowRISC.

Is there any place to get related documents?

I try to add a new instruction and run the simulation using spikes.

I did the following process.

1. make .h file

at  $TOP/riscv-tools/riscv-isa-sim/riscv/insns /

: cp divw.h newinst.h
: gedit newinst.h

require_extension ('M');
require_rv64;
sReg_t lhs = sext32 (RS1);
sReg_t rhs = sext32 (RS2);
if (rhs == 0)
  WRITE_RD (UINT64_MAX);
else
  WRITE_RD (sext32 (lhs + rhs + 100));

And then saved it.

2. Adding opcdoe

at $TOP/riscv-tools/riscv-isa-sim/riscv-tools/riscv-opcodes

: gedit opcodes

newinst rd rs1 rs2 31..25 ​​= 1 14..12 = 1 6..2 = 0x0E 1..0 = 3

I added this phrase.

I did a [make install] and I checked that the instruciton do not overlap.

3. spike rebuild

: cd $ TOP / riscv-tools
: ./build.sh

I'm trying to rebuild a command by executing an error

Then the following error occurred.

In file included from ../riscv/mmu.h:7:0:0,
                 from ../riscv/insn_template.h:3:
../riscv/trap.h: In constructor 'trap_instruction_address_misaligned :: trap_instruction_address_misaligned (reg_t)':
../riscv/trap.h:45:18: error: 'CAUSE_MISALIGNED_FETCH' was not declared in this scope
 DECLARE_MEM_TRAP (CAUSE_MISALIGNED_FETCH, instruction_address_misaligned)
                  ^
../riscv/trap.h:41:41: note: in definition of macro 'DECLARE_MEM_TRAP'
   trap _ ## x (reg_t badvaddr): mem_trap_t (n, badvaddr) {}
                                         ^
../riscv/trap.h: In constructor 'trap_instruction_access_fault :: trap_instruction_access_fault (reg_t)':
../riscv/trap.h:46:18: error: 'CAUSE_FAULT_FETCH' was not declared in this scope
 DECLARE_MEM_TRAP (CAUSE_FAULT_FETCH, instruction_access_fault)
                  ^
../riscv/trap.h:41:41: note: in definition of macro 'DECLARE_MEM_TRAP'
   trap _ ## x (reg_t badvaddr): mem_trap_t (n, badvaddr) {}
                                         ^
../riscv/trap.h: In constructor 'trap_illegal_instruction :: trap_illegal_instruction ()':
../riscv/trap.h:47:14: error: 'CAUSE_ILLEGAL_INSTRUCTION' was not declared in this scope
 DECLARE_TRAP (CAUSE_ILLEGAL_INSTRUCTION, illegal_instruction)

Q : Is there something wrong with the process?
or how can I fix the error and run a new instruction with spike?

Hi!
I would like to test the untethered version risc-v based SoC.

When i clone the repo and proceed to build the toolchain, i get this error, not sure if it's due to my network limitations or to something else?

I would like to understand please if the lowRISC SoC depends on a particular version of riscv-tools (gnu compilation toolchain / spike ...etc)? Or can I use a recent compilation toolchain with an old version of lowRISC? I mean by that if i change my hardware configuration (number of cores / accelerators / cache ...etc) do I need to rebuild the software toolchain/simulators?

Thanks for taking time to respond my questions.
Best regards.

We observed that the verification of the elf in memory hangs occasionally. The verification is temporarily de-activated. Suspects of this issue are:

• The glip UART transport
• The actual physical interface
• The MAM timing

The problem seems only half-way undeterministic. Adding debug probes to get more details is probably a good start.

I spotted a potential deadlock scenario in the release channel design when there are multiple cores contending for the release channel for a single bank.
Setup:
Assuming that there are two cores and four L2 banks. In each L2 bank, we have two acq tracker and one rel tracker.
State:
acqTracker1 is occupying wb unit for back invalidation. The wb is probing cores and wait for their release response (e.g. waiting for release from core 1)
At the same time, acqTracker 0 is also busy with a transaction, and wish to send a request to wb when it returns to idle.
Deadlock:
Now that core 1 is sending a release valid; simultaneously core 0 is sending a voluntary release to the same bank. In addition, core 0's release is in the same set as the addr in acqTracker 0. If the LockingRRArbiter chooses to wire core 0's release to the destination bank, there is a circular dependency that causes deadlock:
Core 0's release is blocked (ready low) because it is in the same cache set as acqTracker0; acqTracker0 is blocked because it is waiting wb to become idle; wb is blocked because it is waiting for core 1's release; core 1's release is blocked because the arbiter is choosing core 0's release ...

I'd appreciate if anyone can help verify if this can indeed lead to a deadlock.
A temp fix I made was to force the TL crossbar lockingArbiter to continuously switch the between valid clients when it is not in locked state. It helped in the workload that originally hangs, but I am not sure if this fix can cause any starvation.

I haven't been able to pin down exactly when things were broken, but I can confirm it's independent of the PTE changes etc that were introduced since the last release. Building debug-v0.3 of lowrisc-chip and then trying to run the isa tests under spike (e.g. with make -C ./riscv-tests/isa/ run) results in failure:

HTIF: attempt to read from illegal address 0x400005c0

I have booted Linux on FPGA and want to run my programs on it.
I use riscv64-unknown-elf-gcc to compile a simple hello world program and copy it into root.bin through make_root.sh. It successfully runs on FPGA.
But when I failed to run spec2000 and got error message like Can't open file *** or Error opening file *** for a access.
Does it due to lack some libraries ?
If I use riscv64-unknown-linux-gnu-gcc as compiler to run hello world , it would show me /bin/ash: ./hello: not found

In fact I encountered the same problem in another respository on vc706. That time I fixed this problem by using riscv64-unknown-linux-gnu-gcc to compile programs into filesystem of vmlinux. But this time I failed to boot linux when I used make ARCH=riscv menuconfig , and got following messages

[    0.230000] TCP: cubic registered
[    0.230000] Freeing unused kernel memory: 1040K (ffffffff80000000 - ffffffff80104000)
[    0.230000] Failed to execute /init (error -8)
[    0.230000] Kernel panic - not syncing: No working init found.  Try passing init= option to kernel. See Linux Documentation/init.txt for guidance.
[    0.230000] CPU: 0 PID: 1 Comm: swapper Not tainted 3.14.41-g9a25e8d-dirty #6
[    0.230000] Call Trace:
[    0.230000] [<ffffffff80105f54>] walk_stackframe+0x0/0xc8
[    0.230000] [<ffffffff802b4ae4>] panic+0xb4/0x1c4
[    0.230000] [<ffffffff802b44f8>] rest_init+0x80/0x84
[    0.230000] [<ffffffff802b45ec>] kernel_init+0xf0/0xf4
[    0.230000] [<ffffffff802b44f8>] rest_init+0x80/0x84
[    0.230000] [<ffffffff802b44f8>] rest_init+0x80/0x84
[    0.230000] [<ffffffff80104bb8>] ret_from_syscall+0x10/0x14

I don't know why failed. Maybe I don't understand which determind the filesystem, root.bin or vmlinux.

Hi, I keep facing the error when I run the

<<CONFIG=Nexys4DebugConfig make selftest>>
it has no problem with <>
so the problems only came at make target. Any advice?

INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:01:05 ; elapsed = 00:01:13 . Memory (MB): peak = 3507.039 ; gain = 0.000 ; free physical = 8960 ; free virtual = 117162
INFO: [Vivado_Tcl 4-395] Unable to parse hwdef file chip_top.hwdef
INFO: [Common 17-206] Exiting Vivado at Mon May 21 10:06:51 2018...
[Mon May 21 10:06:55 2018] impl_1 finished
wait_on_run: Time (s): cpu = 00:00:00.26 ; elapsed = 00:10:15 . Memory (MB): peak = 1052.715 ; gain = 0.000 ; free physical = 11447 ; free virtual = 119649
INFO: [Common 17-206] Exiting Vivado at Mon May 21 10:06:55 2018...
vivado -mode batch -source ../../common/script/search_ramb.tcl -tclargs lowrisc-chip-imp > search-ramb.log
python ../../common/script/bmm_gen.py search-ramb.log src/boot.bmm 128 65536
data2mem -bm src/boot.mem -bd src/boot.mem -bt lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit -o b lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit
/opt/Xilinx/SDK/2015.4/bin/loader: line 164: 16352 Segmentation fault (core dumped) "$RDI_PROG" "$@"
Makefile:200: recipe for target 'lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit' failed
make[1]: *** [lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit] Error 139
make[1]: Leaving directory '/home/mmwong/Documents/lowrisc-chip/fpga/board/nexys4_ddr'
Makefile:230: recipe for target 'selftest' failed
make: *** [selftest] Error 2

The MAM provides the information about the memory regions it can access. This should be configured in chip_top based on the definitions of dev_map.vh and consts.vh.

Hello,

I'm running the make run-vpd in the emulator.
I get the following:
make run-vpd

rm -rf output/rv64ui-p-add.vpd.vcd && mkfifo output/rv64ui-p-add.vpd.vcd
vcd2vpd output/rv64ui-p-add.vpd.vcd output/rv64ui-p-add.vpd > /dev/null &
./emulator-DefaultCPPConfig-debug +dramsim +max-cycles=100000000 +verbose -voutput/rv64ui-p-add.vpd.vcd +loadmem=output/rv64ui-p-add.hex none 3>&1 1>&2 2>&3 | /home/alpha/lowrisc-chip/riscv/bin/spike-dasm  > output/rv64ui-p-add.out && [ $PIPESTATUS -eq 0 ]
/bin/bash: vcd2vpd: command not found

Could you please help me fix it ? Is it necessary to simulate RISCV on Zynq ? Or is there another way ?

Thank you

Hi,

For the lowrisc chip tapeout in 2016, I saw there is block for Wishbone to AXI bridge.

Where can I download this block ?

I hope it is written in Chisel (.scala) so I can extract to verilog.

Thanks,

David

Per the 1.91 Privileged Specification, I found that the behavior of the PC on reset is to be set to "an implementation-defined" default value (see section 3.3). What does this mean for the lowRISC chip?

I checked out the latest source code and built the Hello UART example. Closer inspection of the ELF header revealed the entry point to be 0x40000000 (supported by the linker script for release 0.5).

I went back an earlier release (0.2) and the entry point of the same hello baremetal program was 0x100 (supported by the linker script).

• What is the PC set to on reset for the 0.2 and 0.5 releases? Has it changed over time? Is it planned to change again?
• Is there a fixed ROM loader that jumps to these payload entry points (e.g. the ELF programs)? If so, where is the source for this boot ROM?
• Where can I find the latest system memory map for release 0.5? Is this still accurate from 0.2?
• What is the purpose of BRAM when we have DDR DRAM? In a production system, would BRAM actually be something like Flash since the reset vector is likely somewhere in low memory?

• memory operation commands in trace debugger
• I had to manually increase tlClientXactIdBits to avoid uncached crossbar lost id field.
• test softfloat
• test snooping
• test nasti

[done] memory mapped (XIP) quad SPI flash
[done] try Alex's SPI driver inside Linux and update document (upgrade Linux to 4.6.2)
[done] ISim mem loadelf error with bbl
[done] FPGA mem loadelf unstable
[done] UART read polling and interrupt
[done] Add a wrapper to control the SD reset (power) pin
[done] Feedback from Columbia related to SPI/SD

[partially done] merge nexys video (flash and trace debugger do not work)
[partially done] Automatically add IO devices to configuration string. (waiting further information about configure string)

[NoFix] allow trace debugger to change reset boot address (use jump instead)
[NoFix] Re-factoring on-chip nasti net (wait refactoring from Berkeley)
[NoFix] Support narrower AXI in the NastiIOTileLinkIOConverter (currently does not support 64-bit IO read/write) (wait refactoring from Berkeley)

Currently waiting for the internal VM to be set up.

Any guideline on using rocc with lowrisc rocket chip?
would the procedure similar to that of the rocketchip developed by Berkeley?

Hi,

I am a hw developer and relatively new to open source processors.

Recently I started studying https://github.com/freechipsproject/rocket-chip to get access to open source RISC-V processor. My aim is to understand the core so that I can customize and use it as a part of product idea we have.

As it would be expected, right now I am not very conversant with how everything is organized in the rocket-chip soc and I am relying on any little information I get from web-pages, google group and git-hub Issues page.

I have a general query for you guys.
What are the 'same' and 'different' things between lowrisc-chip and rocket-chip?
Does lowrisc chip in general has more documentation and easier to get hold of?

Thanks
Chinmaya

Would it be possible to use the blackbox for Verilog integration (such as BlackBoxInline, BlackBoxResource utility from Chisel 3) in this version of LowRiscv chip? If not any advice or alternative that could work for this chip?

As I was trying to make a VCS simulator binary (default configuration) from the folder vcs, I have successfully generate the DefaultL2Config-sim. Next I would like to simulate the hello program using PK. I understand from the previous version of tutorial, there are 3 ways to generate the hello program.
There used to be a make file in $TOP/riscv-tools/hello that generates three different executables for all environment but this was not longer available in the latest lowriscv so hence I did the following:

riscv64-unknown-elf-gcc hello.c -o hello

and run with the simulator

./DefaultL2Config-sim pk ex

However, I get the following on the terminal and it just goes on continuously without ending:

C0: 71181 [1] pc=[0000000004] W[r 0=0000000000000008][1] R[r 5=0000000040000000] R[r 0=0000000000000000] inst=[00028067] DASM(00028067)
C0: 71182 [0] pc=[0040000000] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000000] DASM(00000000)
C0: 71187 [1] pc=[0000000000] W[r 5=0000000040000000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[40000297] DASM(40000297)
C0: 71188 [1] pc=[0000000004] W[r 0=0000000000000008][1] R[r 5=0000000040000000] R[r 0=0000000000000000] inst=[00028067] DASM(00028067)
C0: 71189 [0] pc=[0040000000] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000000] DASM(00000000)
C0: 71194 [1] pc=[0000000000] W[r 5=0000000040000000][1] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[40000297] DASM(40000297)
C0: 71195 [1] pc=[0000000004] W[r 0=0000000000000008][1] R[r 5=0000000040000000] R[r 0=0000000000000000] inst=[00028067] DASM(00028067)

Any advice what could have went wrong?
Thanks

Basically all assertion checks in Chisel silently pass! Need more investigation on this. [for record purpose]

at http://www.lowrisc.org/docs/untether-v0.2/linux_compile/
I tried to compile linux along this page, but I run the
$ make ARCH = riscv -j vmlinux
command in the first script block The following message

 CHK include / config / kernel.release
  CHK include / generated / uapi / linux / version.h
  CC scripts / mod / devicetable-offsets.s
  CC scripts / mod / empty.o
riscv64-unknown-linux-gnu-gcc: error: unrecognized command line option '-m64'
riscv64-unknown-linux-gnu-gcc: error: unrecognized command line option '-msoft-float'
scripts / Makefile.build: 204: recipe for target 'scripts / mod / devicetable-offsets.s' failed
make [2]: *** [scripts / mod / devicetable-offsets.sys] Error 1
make [2]: *** Waiting for unfinished jobs ....
riscv64-unknown-linux-gnu-gcc: error: unrecognized command line option '-m64'
riscv64-unknown-linux-gnu-gcc: error: unrecognized command line option '-msoft-float'
scripts / Makefile.build: 308: recipe for target 'scripts / mod / empty.o' failed
make [2]: *** [scripts / mod / empty.o] Error 1
scripts / Makefile.build: 455: recipe for target 'scripts / mod' failed
make [1]: *** [scripts / mod] Error 2
Makefile: 527: recipe for target 'scripts' failed
make: *** [scripts] Error 2

I did not progress anymore as the phrase came up.

Maybe you should modify $ TOP / riscv-tools / linux-3.14.41 / arch / riscv / Makefile. Is there a way?

For reference,
on this page http://www.lowrisc.org/docs/untether-v0.2/
I ran 'Compile and install RISC-V cross-compiler' under '2. The development enviromnet' and
I was following 'Compile the RISC-V Linux and the ramdisk root.bin'.

I don't think this is related to the deadlock issue last time.. But just a bit confused by the irel_can_merge signal in line 895 of acqTracker:

val irel_can_merge = io.irel().conflicts(xact_addr_block) &&
io.irel().isVoluntary() &&
!Vec(s_idle, s_meta_read, s_meta_resp, s_meta_write).contains(state) &&
!all_pending_done &&
!io.outer.grant.fire() &&
!io.inner.grant.fire() &&
!pending_vol_ignt

It doesn't exclude s_busy state, which I think it should.

Consider such scenario: there are multiple idle cycles between voluntary release beats. Suppose the acquire tracker is in s_busy and has just finished the inner grant, waiting for the core finish signal. Now that a voluntary release of the same address comes, so the acqTracker accepts the release. Later, before the second release beat comes, the inner finish signal comes, and the first release beat finishes its write to the data array, so the acqTracker returns to s_idle (should this happen?). In this case, I think one release beat is consumed by acqTracker, and the remaining 7 beats will go to voluntary relTracker, forcing the voluntary relTracker to wait for the last missing beat forever.

Do you think if this will happen?

Hello I am a student studying computer architecture.

I would like to customize the lowRISC chip to apply in my ideas.
I have trouble in checking the simulation results and understanding the entire structure.
so..I need your help.. TT

1. The $ TOP / src / main directory contains the 'verilog' and 'scala' directories. I wonder if they both describe the same thing. When I create a bitstream or simulator, I see only .sv(verilog) in the Makefile (which I may have misunderstood). So what should I do to fix the verilog? Does not the chisel need to be modified?

2. To check the operation of lowRISCV-chip with waveform
   http://www.lowrisc.org/docs/untether-v0.2/vsim/ I proceeded as follows:

cd $ TOP / vsim
make sim-debug
elf2hex 16 4096 rv64ui-p-add> rv64ui-p-add.hex

As a result of executing the third command, the following statement appears.

Assertion `fd! = -1 'failed. If you do not want to use std :: basic_string, you can use std :: basic_string with a long unsigned int> load_elf (const char *, memif_t *)

Is there a way to solve this problem and see the motion waveform of rv64ui-p-add? hlep me .. plz

May I ask what version of RISCV ISA does this chip support? (e.g. the latest version is spec2.2 on UCB RISCV website, but I believe this chip is derived from an older repo and maybe only support older specs)

Thanks!

Some features from the debug-v0.3 release should be merged to minion-v0.4 for better continuity. Such as the recent Zedboard port from Furkan.

Also a contributor files should be provided this time to reflect the external supports we received, such as the Zed port and tagged memory backport.

I will do this soon after I finish documenting the tagged memory.

My lowrisc-chip version: minion-v0.4, vivado version: 2015.4
I want to generate bitstream in kc705 but failed. I got the following message:

Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
ERROR: [Synth 8-1031] dii_package is not declared [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:3]
ERROR: [Synth 8-1766] cannot open include file consts.vh [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:5]
ERROR: [Synth 8-1766] cannot open include file dev_map.vh [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:6]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_MEM_TAG_WIDTH [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:180]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_PADDR_WIDTH [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:181]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_MEM_DAT_WIDTH [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:182]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_IO_TAG_WIDTH [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:485]
ERROR: [Synth 8-2841] use of undefined macro ROCKET_IO_DAT_WIDTH [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:487]
INFO: [Synth 8-2350] module chip_top ignored due to previous errors [/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv:9]
Failed to read verilog '/home/xqz/tmp/lowrisc-chip/src/main/verilog/chip_top.sv'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 0 Warnings, 0 Critical Warnings and 9 Errors encountered.

But I didn't encounter any problem in nexys4_ddr. What's wrong ?

"Load boot.bin into memory" I have stopped at the state. [nexys4_ddr fpga board]

plz... help me

step 1. download pre-built fpga.bit and boot.bin [v0.3]
-> Downloading another version is the same....

step 2. I put fpga.bit and boot.bin on my sdcard

step 3. open the serial terminal

step 4. JP1[USB/SD] Setting and power On

but, don't load a boot.bin... and don't booting linux

It seems to me that the L2 cache implementation in the Uncore is neither inclusive nor exclusive, because the eviction policy doesn't distinguish cached/uncached lines in tile caches. Could you confirm if my understanding is correct or not? Thanks.

Need some change to ask Jenkins to automatically testing PRs as well. [not urgent]

Hello,

I ported the v3 implementation to a ZedBoard, using PMODs for UART and SD Card, and using memory through PS's (Processing System) HP (High Performance) AXI port. The idea is to setup a shared memory region between ARM and RISC-V, introduce the ARM part as a platform device to RISC-V, and go for emulating some peripheral functionalities over ARM to ease device device and driver development.

My port works for basic hello applications, but I cannot pass the dram test. As far as I understand, the "ram.c" test code sets big memory regions to force L1 and L2 caches be filled so that write back to DRAM will occur. So I think my ZedBoard port to use PS's memory has the problem.

As I see that you provide the DRAM code which specifically test the memory write back issue, I thought that you may have observed the same or similar problem before and come up with a test code to verify the solution. Therefore, I would like to kindly ask you if you have any suggestions for me to look at to solve this.

Kind Regards,

Furkan

We should build a generic bootloader, that later will probably be replaced by a secure bootloader in a minion.

But for now it should follow the following precedence:

• Check a specific address on an memory-mapped debug module that overwrites the boot, currently only to "boot from RAM"
• Mount SD and load program to RAM, jump to RAM
• Mount FPGA Flash, load program and jump to RAM