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Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:

Home Page: https://intel.ly/2NiBqcb

Shell 18.16% Tcl 28.63% Batchfile 0.11% Verilog 2.91% C 0.38% C++ 49.80% Coq 0.01%

fpga-devcloud's Introduction

DISCONTINUATION OF PROJECT

This project will no longer be maintained by Intel.
Intel has ceased development and contributions including, but not limited to, maintenance, bug fixes, new releases, or updates, to this project.
Intel no longer accepts patches to this project.
If you have an ongoing need to use this project, are interested in independently developing it, or would like to maintain patches for the open source software community, please create your own fork of this project.

FPGA DESIGN DEVELOPMENT AND WORKLOADS FOR HARDWARE ACCELERATION

Develop programmable solutions and validate your workloads on leading FPGA hardware with tools optimized for Intel technology. Use this cloud solution in the classroom to support acceleration engineering curriculum.

Website | Devcloud Access Instructions | Quickstart Guides | FAQ | Contact Us

Welcome to the Intel FPGA Devcloud GitHub!

For instructions on how to connect to the Devcloud, click on Devcloud Access Instructions.

For access to quick, hands-on guides that will get you started on key features of Intel FPGA Devcloud technology, click on Quickstart Guides.

For answers to commonly asked questions, click FAQ.

fpga-devcloud's People

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fpga-devcloud's Issues

qsub -q batch@v-qsvr-nda -l nodes=1:fpga_compile:ppn=2 -d. build_fpga_hw.sh qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u64771@login-2, queue batch)

i was trying to do intel one API samples, vector add

but at this command submit error is coming ,
qsub -q batch@v-qsvr-nda -l nodes=1:fpga_compile:ppn=2 -d. build_fpga_hw.sh

USM support?

Hi, I'm running the "vector-add" example. With buffers worked excellently but with USM I'm getting:

Running on device: pac_s10 : Intel PAC Platform (pac_ef00000)
Vector size: 10000
Shared memory allocation failure.

Do you know how I can solve this? Is there some FPGA in the DevCloud with USM support? Thank you very much

Timing violation in example - streaming_dma_afu

I have been working on compiling the streaming_dma_afu example on the FPGA devcloud using the Stratix 10 (D5005 PAC card) Devstack version 2.0.1.
On compiling the design, I get timing-violations as given in the Output section of this query. Could anyone please suggest what the issue might be? I was not expecting the violations to exist in the standard example. I'm following the instructions given in the link here.

Environment:

Intel Devcloud
tools_setup: Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL
Quartus Version: Version 19.2.0 Build 57 06/24/2019 Patches 0.01dc SJ Pro Edition
Example: streaming_dma_afu

Output Section:

1) Taken from clocks.sta.fail.summary

Type  : 2_slow_900mv_100c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.249
TNS   : -5.320

Type  : 2_slow_900mv_100c setup 'u0|dcp_iopll|dcp_iopll_clk2x'
Slack : -0.180
TNS   : -11.450

Type  : 2_slow_900mv_0c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.067
TNS   : -0.204

Type  : MIN_fast_900mv_100c setup 'mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk'
Slack : -0.029
TNS   : -0.045

This is the first failing path's details taken from afu_default_2_slow_900mv_0c_setup.rpt file.

Path #1: Setup slack is -0.067 (VIOLATED)
===============================================================================
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Path Summary                                                                                                                                          ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+
; Property           ; Value                                                                                                                            ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+
; From Node          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|out_payload[203] ;
; To Node            ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]                                    ;
; Launch Clock       ; mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk                                                                           ;
; Latch Clock        ; mem|mem_bank[1].emif_ddr4_inst|emif_s10_0_core_usr_clk                                                                           ;
; Data Arrival Time  ; 6.372                                                                                                                            ;
; Data Required Time ; 6.305                                                                                                                            ;
; Slack              ; -0.067 (VIOLATED)                                                                                                                ;
+--------------------+----------------------------------------------------------------------------------------------------------------------------------+

+-----------------------------------------------------------------------------------------+
; Statistics                                                                              ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min    ; Max    ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
; Setup Relationship        ; 3.336  ;       ;             ;            ;        ;        ;
; Clock Skew                ; -0.435 ;       ;             ;            ;        ;        ;
; Data Delay                ; 3.069  ;       ;             ;            ;        ;        ;
; Number of Logic Levels    ;        ; 1     ;             ;            ;        ;        ;
; Physical Delays           ;        ;       ;             ;            ;        ;        ;
;  Arrival Path             ;        ;       ;             ;            ;        ;        ;
;   Clock                   ;        ;       ;             ;            ;        ;        ;
;    Clock Network (Lumped) ;        ; 1     ; 3.199       ; 100        ; 3.199  ; 3.199  ;
;   Data                    ;        ;       ;             ;            ;        ;        ;
;    IC                     ;        ; 1     ; -0.001      ; 0          ; -0.001 ; -0.001 ;
;    Cell                   ;        ; 3     ; 0.078       ; 3          ; 0.000  ; 0.078  ;
;    uTco                   ;        ; 1     ; 0.402       ; 13         ; 0.402  ; 0.402  ;
;    Routing Element        ;        ; 24    ; 2.590       ; 84         ; 0.000  ; 0.211  ;
;  Required Path            ;        ;       ;             ;            ;        ;        ;
;   Clock                   ;        ;       ;             ;            ;        ;        ;
;    Clock Network (Lumped) ;        ; 1     ; 2.131       ; 100        ; 2.131  ; 2.131  ;
+---------------------------+--------+-------+-------------+------------+--------+--------+
Note: Negative delays are omitted from totals when calculating percentages

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Arrival Path                                                                                                                                                                                                                                                                                                 ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location                                   ; Element Type                ; Element                                                                                                                                                                                      ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 0.104   ; 0.104    ;    ;      ;        ;                                            ;                             ; launch edge time                                                                                                                                                                             ;
; 3.303   ; 3.199    ;    ;      ;        ;                                            ;                             ; clock path                                                                                                                                                                                   ;
;   3.303 ;   3.199  ; R  ;      ;        ;                                            ;                             ; clock network delay                                                                                                                                                                          ;
;   3.303 ;   0.000  ;    ;      ; 1      ; EC_X66_Y261_N21                            ; EC                          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|out_payload[203]                                                             ;
; 6.372   ; 3.069    ;    ;      ;        ;                                            ;                             ; data path                                                                                                                                                                                    ;
;   3.705 ;   0.402  ; RR ; uTco ; 2      ; EC_X66_Y261_N21                            ; EC                          ; fpga_top|inst_green_bs|ccip_std_afu|afu_inst|the_streaming_dma_test_system|emif_b_bridge|emif_b_bridge|cmd_fifo|mem_rtl_0|auto_generated|altera_syncram_impl1|ram_block2a202|portbdataout[0] ;
;   3.705 ;   0.000  ; RR ; RE   ; 1      ; EC_X66_Y261_N21                            ; EC                          ; EC                                                                                                                                                                                           ;
;   3.708 ;   0.003  ; RR ; RE   ; 1      ; MEDIUM_EAB_RE_X66_Y261_N0_I111             ; MEDIUM_EAB_RE               ; MEDIUM_EAB_RE                                                                                                                                                                                ;
;   3.897 ;   0.189  ; RR ; RE   ; 1      ; R10_X66_Y261_N0_I19                        ; R10 interconnect            ; H10                                                                                                                                                                                          ;
;   4.005 ;   0.108  ; RR ; RE   ; 1      ; C2_X75_Y259_N0_I30                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   4.140 ;   0.135  ; RR ; RE   ; 1      ; R4_X72_Y260_N0_I53                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   4.140 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X71_Y260_N0_I0 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   4.351 ;   0.211  ; RR ; RE   ; 1      ; C16_X71_Y260_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.519 ;   0.168  ; RR ; RE   ; 1      ; C16_X71_Y276_N0_I27                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.676 ;   0.157  ; RR ; RE   ; 1      ; C16_X71_Y292_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.815 ;   0.139  ; RR ; RE   ; 1      ; C16_X71_Y308_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   4.911 ;   0.096  ; RR ; RE   ; 1      ; R4_X72_Y324_N0_I16                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.007 ;   0.096  ; RR ; RE   ; 1      ; C2_X75_Y324_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.093 ;   0.086  ; RR ; RE   ; 1      ; C2_X75_Y326_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.175 ;   0.082  ; RR ; RE   ; 1      ; C2_X75_Y328_N0_I25                         ; C2 interconnect             ; V2                                                                                                                                                                                           ;
;   5.263 ;   0.088  ; RR ; RE   ; 1      ; R4_X72_Y330_N0_I58                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.398 ;   0.135  ; RR ; RE   ; 1      ; R4_X68_Y330_N0_I50                         ; R4 interconnect             ; H4                                                                                                                                                                                           ;
;   5.398 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X67_Y330_N0_I3 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   5.592 ;   0.194  ; RR ; RE   ; 1      ; C16_X67_Y330_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   5.732 ;   0.140  ; RR ; RE   ; 1      ; C16_X67_Y346_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   5.732 ;   0.000  ; RR ; RE   ; 1      ; R24_C16_INTERCONNECT_DRIVER_X67_Y354_N0_I2 ; R24/C16 interconnect driver ; WIRE_MUX                                                                                                                                                                                     ;
;   5.929 ;   0.197  ; RR ; RE   ; 1      ; C16_X67_Y354_N0_I26                        ; C16 interconnect            ; V16                                                                                                                                                                                          ;
;   6.065 ;   0.136  ; RR ; RE   ; 1      ; C4_X67_Y362_N0_I0                          ; C4 interconnect             ; V4                                                                                                                                                                                           ;
;   6.208 ;   0.143  ; RR ; RE   ; 2      ; LOCAL_INTERCONNECT_X68_Y366_N0_I46         ; Block interconnect          ; LAB_LINE                                                                                                                                                                                     ;
;   6.295 ;   0.087  ; RR ; RE   ; 1      ; LAB_RE_X68_Y366_N0_I13                     ; LAB_RE                      ; leimc1[1]                                                                                                                                                                                    ;
;   6.294 ;   -0.001 ;    ; IC   ; 1      ; LABCELL_X68_Y366_N9                        ; Combinational cell          ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|wr_writedata[0]~138|datac                                                                                            ;
;   6.372 ;   0.078  ; RR ; CELL ; 1      ; LABCELL_X68_Y366_N9                        ; Combinational cell          ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|wr_writedata[0]~138|combout                                                                                          ;
;   6.372 ;   0.000  ; RR ; CELL ; 1      ; FF_X68_Y366_N11                            ; ALM Register                ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]|d                                                                                              ;
;   6.372 ;   0.000  ; RR ; CELL ; 1      ; FF_X68_Y366_N11                            ; ALM Register                ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138]                                                                                                ;
+---------+----------+----+------+--------+--------------------------------------------+-----------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Data Required Path                                                                                                                                                       ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+
; Total   ; Incr     ; RF ; Type ; Fanout ; Location        ; Element Type ; Element                                                                                       ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+
; 3.440   ; 3.440    ;    ;      ;        ;                 ;              ; latch edge time                                                                               ;
; 6.204   ; 2.764    ;    ;      ;        ;                 ;              ; clock path                                                                                    ;
;   5.571 ;   2.131  ; R  ;      ;        ;                 ;              ; clock network delay                                                                           ;
;   6.236 ;   0.665  ;    ;      ;        ;                 ;              ; clock pessimism removed                                                                       ;
;   6.204 ;   -0.032 ;    ;      ;        ;                 ;              ; advanced clock effects                                                                        ;
; 6.174   ; -0.030   ;    ;      ;        ;                 ;              ; clock uncertainty                                                                             ;
; 6.305   ; 0.131    ;    ; uTsu ; 1      ; FF_X68_Y366_N11 ; ALM Register ; fpga_top|inst_green_bs|lm_pipe[1].local_mem_avmm_bridge|ddr_avmm_bridge|cmd_writedata[1][138] ;
+---------+----------+----+------+--------+-----------------+--------------+-----------------------------------------------------------------------------------------------+

Specified license file does not exist for Quartus Prime Standard

I am trying to run the Quartus Prime Standard edition on one of the compile servers.

Steps I took:

Use tools_setup to specify Quartus Prime Standard.

$ tools_setup 

Which tool would you like to source?
1) Quartus Prime Lite
2) Quartus Prime Standard
3) Quartus Prime Pro
4) HLS
5) Arria 10 PAC Compilation and Programming - RTL AFU, OpenCL
6) Arria 10 - OneAPI, OpenVINO
7) Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL
8) Stratix 10 - OneAPI, OpenVINO

Number: 2
sourcing /glob/development-tools/versions/intelFPGA/18.1/init_quartus.sh

Overwrite $QUARTUS_ROOTDIR_OVERRIDE which is still set to Quartus Pro.

$ echo $QUARTUS_ROOTDIR_OVERRIDE
/glob/development-tools/versions/oneapi/2022.1.2/oneapi/intelfpgadpcpp/2022.1.0/QuartusPrimePro/19.2/quartus
$ export QUARTUS_ROOTDIR_OVERRIDE=/glob/development-tools/versions/intelFPGA/18.1/quartus

Run quartus_map in my project

$ quartus_map otma_bringup
Error (292026): Specified license file does not exist.

Trying a different license file also leads to an error

$ echo $LM_LICENSE_FILE
/usr/local/licenseserver/quartus.lic
$ export LM_LICENSE_FILE=/usr/local/licenseserver/psxe.lic
$ quartus_map otma_bringup
Error (292027): Specified license does not contain information required to run the Quartus Prime software.

I'm assuming the psxe.lic is not the proper license file for Quartus Prime but what is the location of the correct license file?

$OPAE_PLATFORM_ROOT and some other shell variables are not set for new users

Hi,
it seems that some variables like $OPAE_PLATFORM_ROOT are not set for new users. I think it would be very helpful, if you add a short sentence about sourcing the correct file (/glob/development-tools/versions/fpgasupportstack/a10/1.2/inteldevstack/init_env.sh) to set these variables.

Compilation generated invalid bitstream with Arria10 PAC on devcloud

I tried compiling an OpenCL kernel on Arria10, it resulted in an invalid bitstream (.aocx) with errors when I tried fusing the bitstream onto the board. Upon checking the logfiles kernel_name.log, I observed that qsys scripts were not running and the corresponding output was absent in the log-file. This was the same issue with all the nodes, which wasn't the case when compiled with Stratix10. Attaching the screenshots of the log with compilation on Arria10 and Stratix10.

gdb Support

Hello,
Is it possible to provide access to gdb in the Arria/Stratix nodes to debug opencl developed codes?

PAC10 Batch Compilation

I'm trying to use the OpenCL flow for PAC10 (Arria10)

The quick start guide
https://github.com/intel/FPGA-Devcloud/tree/master/main/QuickStartGuides/OpenCL_Program_PAC_Quickstart/Arria%2010

explains how to login and compile for such device. The problem (as I understand) is that it works for an interactive session by using the devcloud_login interactive script.

I've tried to replicate the commands done in the script to get a batch session to compile for PAC10 without luck.

Could you provide an example to send a compilation batch job to the queue?

sys/cdefs.h: No such file or directory on A10, oneAPI (A10/S10) nodes

Hi,

I am trying to compile some c++. the compilation worked well on S10 node, but after switching to any other node, I will get the following error:

In file included from /home/u96851/t2sp/install/gcc-7.5.0/include/c++/7.5.0/x86_64-pc-linux-gnu/bits/os_defines.h:39:0,
                 from /home/u96851/t2sp/install/gcc-7.5.0/include/c++/7.5.0/x86_64-pc-linux-gnu/bits/c++config.h:533,
                 from /home/u96851/t2sp/install/gcc-7.5.0/include/c++/7.5.0/string:38,
                 from /home/u96851/t2sp/Halide/src/Expr.h:8,
                 from /home/u96851/t2sp/Halide/src/AddAtomicMutex.h:4,
                 from /home/u96851/t2sp/Halide/src/AddAtomicMutex.cpp:1:
/usr/include/features.h:424:12: fatal error: sys/cdefs.h: No such file or directory
 #  include <sys/cdefs.h>
            ^~~~~~~~~~~~~
compilation terminated.

It seems like some libraries are missing on A10 and oneAPI nodes, according to this thread? Can you please install that on these nodes? Thanks

qsub error

im using putty and I want to submit a vasp work but when i enter qsub i receive an error like this: qsub: Unauthorized Request MSG=group ACL is not satisfied: user *** login-3.local, queue hpc

can anyone please help with this? tnx

qsub error qsub: Unauthorized Request MSG=group ACL is not satisfied: user *** @login-3.local, queue hpc

Shutdowm after running ./host

Hi, I tried running the example, and all works fine until I finished compiling part 3.4. When I run the "./host" code in part 3.5 Running the host code, my session get terminated and went straight back to login node 2.

Is it expected? As I tried 3 times and all ended up same. Can you provide some guidance?

Thank you.

Increase the number of hugepages available to users

Currentl, the S10 systems limit the user to 20 hugepages:
s001-n189:~$ sysctl vm.nr_hugepages vm.nr_hugepages = 20

Is there a way to increase this for the user, or can it be set to default to 256? With some designs using multiple dma channels, we are currently maxing out at 92 hugepages, but future designs will use significantly more.

ssh devcloud permission denied

Hi,

I cannot login to the devcloud server. I got the following error msg

$ ssh devcloud
Permission denied (publickey,gssapi-keyex,gssapi-with-mic).
ssh_exchange_identification: Connection closed by remote host

It seems that my account has expired. How can I renew my account? My account number is u43471.

Thanks

Add additional devices to quartus installation

Would it be possible to add devices like the Stratix V and others?
Currently since the glob directory is read only it is not possible for users to install additional devices.
There might be local workarounds but central installation would be the simplest approach from a user perspective.
Therefore I was wondering whether you (as admins) would consider adding more devices.

Background:
As a student powerfull (used) FPGAs are usually decently accessible but the costs for a powerful server plus the quartus license are quite prohibitive for bigger student projects.
The Arria X and Stratix X are amazing devices but for some projects it's more useful to have an FPGA that is physically accessible.
As far as I'm aware Xilinx provides a decent alternative by letting students use their AWS F1 instances which provide a version of Vivado which is not locked to device families.

DESim VPI source code

Hi,

Is there any chance of uploading the VPI source code in the hardware simulator: https://github.com/intel/FPGA-Devcloud/tree/master/main/HandsFree/Simulator/DESim

We would like to make the simulator compatible for students on Linux.

Thanks

qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u0000@login-2, queue batch)

Reference - issue #10

@llandis , Could you please add me into C009-fpga, I'm not able to get - Arria 10 PAC Compilation and Programming - RTL AFU, OpenCL
Only able to login oneAPI Arria 10 node

Stratix10 PAC spec

Is this SX 2800 spec of stratix10 in devcloud? SOC fpga?
Share devcloud stratix10 PAC spec details

x2goclient prompts for password

@llandis , Please help me to fix this. (Logged in fpga DevCloud node.)

qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u0000@login-2, queue batch)

I was trying to login to S10 node with devclou_login scripts on DevCloud provided here: https://github.com/intel/FPGA-Devcloud/blob/master/main/Devcloud_Access_Instructions/LoginScript/devcloudLoginToolSetup.sh

However qsub failed to process the request. Full error message:

running: qsub -q batch@v-qsvr-fpga -I -l nodes=s001-n138:ppn=2
qsub: submit error (Unauthorized Request  MSG=group ACL is not satisfied: user u0000@login-2, queue batch)

vasp 5.4.4. patch

Hello
i want to download vasp patch 5.4.4 but I cant do it in my region
can anyone please download and send it to my email? tnx
[email protected]

it won't work - any ideas?

########################################################################

u155004@s005-n003:~$ tools_setup
tools_setup: command not found
u155004@s005-n003:~$ ls
tmp
u155004@s005-n003:~$ tools_setup
tools_setup: command not found
u155004@s005-n003:~$ mkdir A10_OPENCL_AFU
u155004@s005-n003:~$ cp -r /opt/intelFPGA_pro/quartus_19.2.0b57/hld/examples_aoc/hello_world A10_OPENCL_AFU
 /opt/intelFPGA_pro/quartus_19.2.0b57/hld/examples_aoc/common A10_OPENCL_AFU
cd A10_OPENCL_AFUu155004@s005-n003:~$ cp -r /opt/intelFPGA_pro/quartus_19.2.0b57/common A10_OPENCL_AFU
u155004@s005-n003:~$ cd A10_OPENCL_AFU
u155004@s005-n003:~/A10_OPENCL_AFU$ aocl diagnose
aocl: command not found

Error enumerating AFCs: not found

Hi,

I am trying to run this oneAPI example on devcloud: https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/DesignPatterns/zero_copy_data_transfer

The compilation worked fine. the host binary and FPGA bitstream are generated successfully. However, when running the binary on real FPGA on devcloud, I got the following error

u68165@s001-n143:~/oneAPI-samples/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/build$ ./zero_copy_data_transfer.fpga 
Error enumerating AFCs: not found
Error enumerating AFCs: not found
Error enumerating AFCs: not found
Error enumerating AFCs: not found
Segmentation fault

I thought this might be caused by environment settings, so I run tools_setup command to set up the environment. After doing that, I got a different error

u68165@s001-n143:~/oneAPI-samples/DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/zero_copy_data_transfer/build$ ./zero_copy_data_transfer.fpga 
Caught a SYCL host exception:
No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (CL_DEVICE_NOT_FOUND)
If you are targeting an FPGA, please ensure that your system has a correctly configured FPGA board.
Run sys_check in the oneAPI root directory to verify.
If you are targeting the FPGA emulator, compile with -DFPGA_EMULATOR.
terminate called after throwing an instance of 'cl::sycl::runtime_error'
  what():  No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (CL_DEVICE_NOT_FOUND)
Aborted

Any thoughts how to fix this error?

x2gosever is not supported by all nodes

X2goserver is not installed on all nodes listed by the devcloud_login function in devcloudLoginToolSetup.sh.

For example, s001-n137,n138 and n139 do support x2go, but s005-n007, s001-n081, n082 ... do not support x2gosever. If working with a node not installed x2goserver, we face an error as attaced.

Please make it enable on all nodes or clarify which compute nodes support x2go in the doc.

Thanks!

Power analysis flow for OpenCL designs

Hi,
Is there any way to perform power analysis (for example, using quartus_pow) for opencl projects?
I tried to follow some instructions at Intel Community ([https://community.intel.com/t5/Intel-Quartus-Prime-Software/Power-analysis-flow-from-OpenCL/m-p/12520] and [https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-analyze-the-power-of-OpenCL-code-in-Arria-10/m-p/206284]) but the files mentioned in those issues (top.qpf and file.pow.summary) don't exist in the opencl output folder.
There is one .qpf file in the folder, name dcp.qpf, but when I run quartus_pow dcp.qpf, this error occurs:

Info: Command: quartus_pow dcp.pf
Info (16677): Loading final database
Error (16546): Cannot load final database - ensure all earlier stages of the compiler have completed.

I'm using arria 10 1.2 nodes in the FPGA-devcloud

Test Entry

ONEAPI_devcloud_login

sign_aocx.sh is failing for Arria10 OpenCL nodes in devcloud.

Previously the script used to work.But now it is not working and returning the following error by exitting the node.
u93923@s005-n007:~/prithvi/stream_yolo/stream_yolo/bin$ source $AOCL_BOARD_PACKAGE_ROOT/linux64/libexec/sign_aocx.sh -H openssl_manager -i stream_yolo_signed.aocx -r NULL -k NULL-o stream_yolo.aocx
The script assumes the PACsign and Intel Acceleration Stack environment is setup. If not run the command : <stack_installation_path>/init_env.sh
hsm_manager=openssl_manager
aocx filename/path=stream_yolo_signed.aocx
root_public_key=NULL
csk_public_key=NULL-o

USAGE:

For creating signed aocx run command :
./sign_aocx.sh [[[-H hsm_manager] [-i input_file ] [-r rootpublickey][-k cskkey] [-o output_file]]]| [-h]]
For creating unsigned images run command :
./sign_aocx.sh [[[-H hsm_manager] [-i file ] [-r NULL] [-k NULL] [-o output_file]

qsub: job 25884.v-qsvr-fpga.aidevcloud completed
u93923@login-2:~$

running: qsub -q batch@v-qsvr-fpga -I -l nodes=s005-n007:ppn=2 qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u75615@login-2, queue batch)

Dear @llandis
Please add me to group c009-fpga
My user id is 75615. I am unable to access Intel Arria10 and Stratix10 for OpenCL.

u75615@login-2:~$ groups
u75615 c009

thanks,
Prithvi.

login script does not work from folder other that $HOME

You have to change the script to eliminate all relative references to nodes.txt file and use smth like
NODE_FILE_TXT=$HOME/nodes.txt

Also you have to add
-d .
at the end of qsub command to stay in same folder after invoking qsub

README adjusts

I have a number of edits to README to consider. I do not have permission to create a branch - so I can't propose via a pull request. Please advise how I might submit a change proposal. https://github.com/jamesreinders/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#readme

Error while executing python code on devcloud: killed python file

I'm trying to execute a python file on devcloud. The job script job.sh is as follows:

#!/bin/bash
source /opt/intel/inteloneapi/setvars.sh > /dev/null 2>&1
python master.py

I am assigning it using the command on Mac terminal:

qsub -l nodes=1:xeon:batch:ppn=2 -d . job.sh

The job ran for something around 3 hours and produced 2 output files: job.sh.e934264 & job.sh.o934264

The job.sh.e934264 file is as follows:

2021-07-26 03:49:45.014693: W tensorflow/stream_executor/platform/default/dso_loader.cc:64] Could not load dynamic library 'libcudart.so.11.0'; dlerror: libcudart.so.11.0: cannot open shared object file: No such file or directory; LD_LIBRARY_PATH: /glob/development-tools/versions/oneapi/2021.3/inteloneapi/vpl/2021.4.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/tbb/2021.3.0/env/../lib/intel64/gcc4.8:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/rkcommon/1.6.1/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ospray_studio/0.7.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ospray/2.6.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/openvkl/0.13.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/oidn/1.4.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//libfabric/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//lib/release:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mkl/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/itac/2021.3.0/slib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ipp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ippcp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ipp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/embree/3.13.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/dnnl/2021.3.0/cpu_dpcpp_gpu_dpcpp/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/gdb/intel64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/libipt/intel64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/dep/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/dal/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/x64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/emu:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/oclfpga/host/linux64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/oclfpga/linux64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/compiler/lib/intel64_lin:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ccl/2021.3.0/lib/cpu_gpu_dpcpp
2021-07-26 03:49:45.014777: I tensorflow/stream_executor/cuda/cudart_stub.cc:29] Ignore above cudart dlerror if you do not have a GPU set up on your machine.
2021-07-26 03:49:50.062319: W tensorflow/stream_executor/platform/default/dso_loader.cc:64] Could not load dynamic library 'libcuda.so.1'; dlerror: libcuda.so.1: cannot open shared object file: No such file or directory; LD_LIBRARY_PATH: /glob/development-tools/versions/oneapi/2021.3/inteloneapi/vpl/2021.4.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/tbb/2021.3.0/env/../lib/intel64/gcc4.8:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/rkcommon/1.6.1/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ospray_studio/0.7.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ospray/2.6.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/openvkl/0.13.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/oidn/1.4.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//libfabric/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//lib/release:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mpi/2021.2.0//lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/mkl/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/itac/2021.3.0/slib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ipp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ippcp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ipp/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/embree/3.13.0/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/dnnl/2021.3.0/cpu_dpcpp_gpu_dpcpp/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/gdb/intel64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/libipt/intel64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/debugger/10.1.2/dep/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/dal/2021.3.0/lib/intel64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/x64:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/emu:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/oclfpga/host/linux64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/lib/oclfpga/linux64/lib:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/compiler/2021.3.0/linux/compiler/lib/intel64_lin:/glob/development-tools/versions/oneapi/2021.3/inteloneapi/ccl/2021.3.0/lib/cpu_gpu_dpcpp
2021-07-26 03:49:50.062403: W tensorflow/stream_executor/cuda/cuda_driver.cc:326] failed call to cuInit: UNKNOWN ERROR (303)
2021-07-26 03:49:50.062449: I tensorflow/stream_executor/cuda/cuda_diagnostics.cc:156] kernel driver does not appear to be running on this host (s001-n061): /proc/driver/nvidia/version does not exist
2021-07-26 03:49:50.062948: I tensorflow/core/platform/cpu_feature_guard.cc:142] This TensorFlow binary is optimized with oneAPI Deep Neural Network Library (oneDNN) to use the following CPU instructions in performance-critical operations: AVX2 AVX512F FMA To enable them in other operations, rebuild TensorFlow with the appropriate compiler flags.
2021-07-26 03:52:31.660446: I tensorflow/compiler/mlir/mlir_graph_optimization_pass.cc:176] None of the MLIR Optimization Passes are enabled (registered 2)
2021-07-26 03:52:31.679568: I tensorflow/core/platform/profile_utils/cpu_utils.cc:114] CPU Frequency: 3400000000 Hz /var/spool/torque/mom_priv/jobs/934264.v-qsvr-1.aidevcloud.SC: line 4: 110188 Killed python master.py

job.sh.o934264 is:

########################################################################
Date: Mon 26 Jul 2021 03:49:38 AM PDT
Job ID: 934264.v-qsvr-1.aidevcloud
User: u65358
Resources: neednodes=1:xeon:batch:ppn=2,nodes=1:xeon:batch:ppn=2,walltime=06:00:00
########################################################################

########################################################################
End of output for job 934264.v-qsvr-1.aidevcloud
Date: Mon 26 Jul 2021 06:52:21 AM PDT
########################################################################

The desired output and code weren't produced and I am facing this issue/error. Can someone please help me with this? Thanks