Comments (2)
Sorry, I realize this was described here
https://github.com/intel/FPGA-Devcloud/tree/master/main/Devcloud_Access_Instructions#54-submitting-batch-jobs
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Ok glad you found batch scripts in the documentation. Note there was an issue with PACSign in batch mode that was recently fixed. Let us know if it works out for you. Thanks
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Related Issues (20)
- Stratix10 PAC spec HOT 1
- ssh devcloud permission denied HOT 3
- Power analysis flow for OpenCL designs
- Increase the number of hugepages available to users HOT 1
- qsub -q batch@v-qsvr-nda -l nodes=1:fpga_compile:ppn=2 -d. build_fpga_hw.sh qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u64771@login-2, queue batch) HOT 2
- DESim VPI source code HOT 3
- Shutdowm after running ./host
- README adjusts
- Error enumerating AFCs: not found
- running: qsub -q batch@v-qsvr-fpga -I -l nodes=s005-n007:ppn=2 qsub: submit error (Unauthorized Request MSG=group ACL is not satisfied: user u75615@login-2, queue batch) HOT 3
- Compilation generated invalid bitstream with Arria10 PAC on devcloud HOT 1
- Error while executing python code on devcloud: killed python file
- sign_aocx.sh is failing for Arria10 OpenCL nodes in devcloud. HOT 3
- sys/cdefs.h: No such file or directory on A10, oneAPI (A10/S10) nodes
- Specified license file does not exist for Quartus Prime Standard HOT 4
- Add additional devices to quartus installation HOT 2
- it won't work - any ideas? HOT 1
- USM support?
- qsub error
- vasp 5.4.4. patch
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