Timing violation in example - streaming_dma_afu about fpga-devcloud HOT 2 OPEN

These "shouldn't" come up. However worst case is worst process voltage temperature and the cards run in a cooled environment with carefully regulated voltage so the chance of seeing worst case silicon process along with edge conditions for voltage and temperature for this negative slack to cause incorrect results are somewhat low but not impossible. We'll look into it. Thanks for bringing this to our attention.
Kind Regards
Larry

from fpga-devcloud.

@llandis

Hi Larry

Thanks for your prompt reply. Look forward to your response re the cause of the problem.

Meanwhile, could you please let me know if there is an "official" way of doing things (eg: specific versions of Quartus and OPAE to be used together) or perhaps a restricted subset of corner cases to timing analyze so that the Intel supplied design compiles without any timing violations.

Regards,
Sneha

from fpga-devcloud.