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View Code? Open in Web Editor NEWCNN acceleration on virtex-7 FPGA with verilog HDL
CNN acceleration on virtex-7 FPGA with verilog HDL
楼主,你好,请问怎么烧录到板子里?不需要约束文件吗?
HI,
I would like to know where I should edit for my own CNN?
Thanks!
楼主,你好,请问你的max_output中,为什么判断完cnt==11后,还要执行cnt<=11,这样cnt不就一直保持11,不再变化了吗,可以详细解释一下嘛
m_layer_input_1.v中,例化的bias_mult2,和ind_conv_in代表什么意思?
m_layer_input_1.v 进行的是什么处理,看了好久,没太看明白,加偏置? 为什么注释里还有“索引做乘法” 这边做乘法是什么意思呢,希望大佬能给讲一下这个程序的思路,缺失两个例化,实在是不懂
谢谢啦
博主你好,我有问题请教,以及把问题发到你的163邮箱了,请你看一下呢
在m_conv_5.v文件中第122行
mult_16 u1(.clk(clk_in),.ce(~(rst_n && rst_tmp3)),.p(mult_tmp),.a(map_in),.b(k_in));
需要调用mult_16模块,但是好像你上传的文件中没有该模块,感谢解答
你好,能否上传一下ram读取的文件,m_conv_3_ram,不太清楚里面是如何实现的,谢谢。
包括各个层的例化参数如bias_mult,ind_max_in,max_ram等等,感谢!
Although ISE can generate these modules, how about the specific configuration parameters? Can you give detailed configuration parameters?Thank you!
您好,想请问下有网络训练的反向传播过程的Matlab代码吗?
您好,您的分享很棒。在Vivado上面跑通了。有些关于优化代码以及算法的问题,想请教您,不知方便不?
微信:chenyirora。期待!!!
比如这里bias_mult3 u2(.clk(clk_in),.ce(~rst_n),.p(bias),.a(ind_cnt2));只有输入a 呀。请问是乘了一个固定的数吗?这个固定的数在那几个bias_mult模块里面各是多少呀!
你好:
对fpga感兴趣,正在调研
请问你用的fpga板子大概多少钱,是什么芯片
它跑forward的速度能更具体的描述吗,比如多大的图片,和gtx1080比较性能上是多少倍的关系
方便的话能加个微信啥的吗?
非常感谢!
Hello Sir
When i am trying to compile the source files present in the "v7-415t_0.5ms" directory, I am getting the following error:
ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_0.v" Line 65: Instantiating <u1> from unknown module <im_in> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_conv_1_1.v" Line 302: Instantiating <m1> from unknown module <mult_16> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_1.v" Line 170: Instantiating <u1> from unknown module <clk_div> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_2.v" Line 198: Instantiating <u2> from unknown module <bias_mult3> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/k2_out.v" Line 70: Instantiating <u1> from unknown module <k_ind_mult> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_3.v" Line 183: Instantiating <u2> from unknown module <bias_mult4> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_4.v" Line 146: Instantiating <u1> from unknown module <m_max_4_ram> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/k3_out.v" Line 73: Instantiating <u1> from unknown module <k_ind_mult2> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_layer_input_5.v" Line 97: Instantiating <u1> from unknown module <m_conv_5_ram> ERROR:HDLCompiler:1654 - "C:/Users/TEJAS/Documents/convolution_network_on_FPGA-master/v7-485t_0.3ms/m_fc.v" Line 96: Instantiating <u1> from unknown module <k_ind_mult3>
Can you please tell me if these modules are missing from the source or they are IPs.If they are IPs , please tell me the mames of those.
Thanks
能给下k_ind_mult u1(.clk(clk_in),.ce(~rst_n),.p(addr_k_tmp),.a(k_ind));的模块说明吗?这个没看懂,乘法器有这样的?
你好,计算索引的几个例化模块再文件夹里找不到
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