gongyanhui Goto Github PK
Name: DavidGong
Type: User
Bio: Machine Learninger
Location: Beijing
DavidGong's Projects
accelerating-cnn-with-fpga
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
aic1106-ipcore
The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example
axi
AXI4 and AXI4-Lite interface definitions and testbench utilities
bladerf-dvbs2
16-APSK DVB-S2 Transmitter for BladeRF
common_cells
Common SV components
convolution_network_on_fpga
CNN acceleration on virtex-7 FPGA with verilog HDL
deep-learning-from-scratch
Six snippets of code that made deep learning what it is today.
embeddedteam
Embedded Team documents, how-to, trainings, etc...
fmin
Unconstrained function minimization in Javascript
free5gran
free5GRAN is an open-source 5G RAN stack. The current version includes a receiver which decodes MIB & SIB1 data. It also acts as a cell scanner. free5GRAN works in SA mode.
hdl
HDL libraries and projects
hlx_examples
Open Source HLx Examples
mobilenet-in-fpga
Generator of verilog description for FPGA MobileNet implementation
npu_on_fpga
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
poc
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
sudoku-norvig
Sudoku solvers in Python, Clojure, Haskell, Ruby, etc. Based on Peter Norvig's constraint propagation and search algorithm.
tlk2501-fpga
Automatically exported from code.google.com/p/tlk2501-fpga
verilog-axi
Verilog AXI components for FPGA implementation
verilog-ethernet
Verilog Ethernet components for FPGA implementation
xiangqi
Chinese chess, a strategy board game for two players.
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