Can you please add support for this board DSDB.

assuming that init.tcl is to be placed in Vivado installation directory, this file is deprecated.

Can anyone tell me the complete process and the different ways with steps involved in interfacing a Pmod BLE bluetooth module to a zynq-z7000 zedboard (USING VIVADO) and transmit/receive data through it?

*This is the first time I am working on a FPGA.

The mig.prj file is missing for the Genesys ZU Board:

Genesys-ZU-3EG

https://github.com/Digilent/vivado-boards/tree/master/new/board_files/genesys-zu-3eg/B.0

I am using the Nexys A7-100T board. In the project property summary, the board is shown installed, but there is no connector.
Also in the Source of the Block Design window, only the source, signal, design tabs are displayed. There is no "board" tab. How do I add the board tab?

I have encountered an error when running C synthesis on the Arty A7-35T. There seems to be an extra -i in the board name, which causes Vitis to not find the board's files.

I have reinstalled board files, but it does not fix this issue.

Starting C synthesis ...
F:/Xilinx/Vitis/2020.1/bin/vitis_hls.bat F:/basic_blink_hls/solution1/csynth.tcl
INFO: [HLS 200-10] Running 'F:/Xilinx/Vitis/2020.1/bin/unwrapped/win64.o/vitis_hls.exe'
INFO: [HLS 200-10] For user 'irfan' on host 'dr-irfan' (Windows NT_amd64 version 6.2) on Thu Feb 09 19:55:56 +0530 2023
INFO: [HLS 200-10] In directory 'F:/'
Sourcing Tcl script 'F:/basic_blink_hls/solution1/csynth.tcl'
INFO: [HLS 200-10] Opening project 'F:/basic_blink_hls'.
INFO: [HLS 200-10] Adding design file 'basic_blink_hls/led_blink.c' to the project
INFO: [HLS 200-10] Opening solution 'F:/basic_blink_hls/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
ERROR: [HLS 200-1023] Part 'xc7a35ticsg324-1L-i' is not installed.
command 'ap_source' returned error code
    while executing
"source F:/basic_blink_hls/solution1/csynth.tcl"
    invoked from within
"hls::main F:/basic_blink_hls/solution1/csynth.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C synthesis.

It would be great if you could add a board file for the new PYNQ-Z1.

Currently the GPIO interface for the shield connector connects the pin one would expect to be connected to IO10 to the SS pin on the SPI connector. This is because the SPI interface is now using IO10 for the SS signal in order to be compatible with the Multi touch display shield (and other digilent shields). Switching the 11th pin in the GPIO interface to connect to the SS pin (where the SPI interface SS pin used to be connected) allows both the shield GPIO and shield SPI interfaces to be used in the same design. The main motivation to move forward with this quick fix (commit f8b2758) was to fix the Arty BSD project.

This is not an ideal solution because someone not using the SPI interface but that is using the GPIO interface probably expects the 11th GPIO bit to control IO10, not the SS pin of the SPI connector. I propose we should identify a better solution that fixes this.

How to use board files (device drivers) of Artix A7 in vivado. I 'm unable to find the .xpr format file in the board supported files.
I able to write a simple led blinking code and executing as well. but how to use the board supported files.

Hello,

Don't know if it's really an issue in the configuration. I'm a newbie with Vivado and ZYNQ devices.
Vivado 2018.3 reports four criticial warnings when I validate the design:

[PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.050 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 has negative value -0.044 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-3] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.035 . PS DDR interfaces might fail when entering negative DQS skew values.
[PSU-4] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.100 . PS DDR interfaces might fail when entering negative DQS skew values.

Are these values correct and can I ignore these warnings?
.
Thanks in advance!

In G2 mig.prj:18
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
Shouldn't it be 40 Ohms?

For both the Arty Z7-10 and Z7-20, the part0_pins.xml files both have incorrect assignments for IO10 and CK_SS.
F16 is CK_SS, and T16 is IO10, according to XDC file and schematic.
F16 is IO10, and T16 is CK_SS, according to (bad) XML part0_pins.xml files.

The Zedboard LEDs do not work when using the board files on Vivado 2018.2. Following the instructions here, the LEDs do not change when the switches are flipped, as expected. Switching the board to the built in board files, which list Avnet as the distributor instead, everything functions just fine.

I believe this is related to these lines, which set up the LEDs to be connected to tristates. They are not present in the Avnet board files.

Hi there!

I am running Vivado 2021.2 (64-bit) SW Build 3367213 on an Ubuntu 20.04 x86_64 PC and run into the following error message (extracted from vivado.log) when parsing the board_files provided in this Repo:

WARNING: [Board 49-26] cannot add Board Part digilentinc.com:zybo-z7-10:part0:1.0 available at /tools/Xilinx/Vivado/2021.2/data/boards/board_files/zybo-z7-10/A.0/board.xml as part xc7z010clg400-1 specified in board_part file is either invalid or not available

I try to setup a Zybo-Z7-10 board. Sadly the error is the same for all Zybo boards, only the Arty and Spartan boards are available within Vivado.

when i add new IP...(ZYNQ7 Processing System) i receive warning [BD 41-176] The physical port 'S_AXI_GP2_rd_socket' specified in the portmap, is not found on the block!
I think this is what causes my code to fail.
Is it right? Please help me fix it. Thanks

Correct frequency is 33.333333 MHz.

Can you help me add the Kintex-7 FPGA (XC7K325T-2FFG900C) digilent board files in the Vivado 2022.1 version? Which version should i use for installing the board files?

Are there official Digilent board files available for the NetFPGA-1G-CML?

It seems the most recent versions of the zybo z7 preset.xml have some invalid syntax. When running board automation in a new block design the ps7 doesn't have any peripherals mapped. Rolling back to an older version of the preset files seems to make things work again.

ss_i component pin "is not used in any mode": https://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf, page 19

this needs to be connected to the spisel pin (page 21 in datasheet).

Out of the box, Zedboard board files have MDIO on EMIO instead of MIO as board is configured

Does anyone have these board files? Maybe in a different repository?
Thanks!

Vivado 2017.4 WebPack cannot see Arty-s7-25 files but it can see Arty-s7-50 just fine

While I'm not sure if the revision made any changes that matter, there are no board files in this repo for the Arty S7-50 revision E board.

There are some problems with the board files where they don't configure IP blocks correctly. Work is being done to fix this

I can see the board listed under the list of board when start a new vivado project and select board (instead of part, like in UG871 v2016.4
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug871-vivado-high-level-synthesis-tutorial.pdf

page 222, specify vivado project details), after following the pynq-z1 documentaion (copy the board files to specified folder of vivado path); it works like other xilinx board (like ZC702 eval board).

But, the board is not listed in the drop down list as presets when I do config Zynq AP SOC ( as in the same UG, page 229, like zc702 listed). I did see the preset file in the same board def files (zipped), and even tried to load it (import xps settings).

Without doing it successfully, I can not even run a hello word demo which needs to use UART (aparently, the usb/UART is on the pynq-z1 board).

Any procedure to follow so I Can have the board listed in the drop-down list in the projectsettings and in the presets?
Thanks,

As the title, I cannot see Nexys 4 board in the list of available boards on Vivado 2019.1.
I've copied the "new\board_files" folder content in the Vivado folder "C:\Xilinx\Vivado\2019.1\data\boards\board_files".

part of code in board.xml of Genesys2 from Line412 to Line435 is not required. It should be removed?

		  <port_map logical_port="TRI_I" physical_port="led_8bits_tri_o" dir="in" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
            </pin_maps>
          </port_map>
		  <port_map logical_port="TRI_O" physical_port="led_8bits_tri_o" dir="out" left="7" right="0"> 
            <pin_maps>
              <pin_map port_index="0" component_pin="led_8bits_tri_o_0"/> 
              <pin_map port_index="1" component_pin="led_8bits_tri_o_1"/> 
              <pin_map port_index="2" component_pin="led_8bits_tri_o_2"/> 
              <pin_map port_index="3" component_pin="led_8bits_tri_o_3"/> 
              <pin_map port_index="4" component_pin="led_8bits_tri_o_4"/> 
              <pin_map port_index="5" component_pin="led_8bits_tri_o_5"/> 
              <pin_map port_index="6" component_pin="led_8bits_tri_o_6"/> 
              <pin_map port_index="7" component_pin="led_8bits_tri_o_7"/> 
            </pin_maps>
          </port_map>

Links of the boards are broken. Here is an example:

Board links to:
https://reference.digilentinc.com/programmable-logic/cmod-s7/start

When it should link to:
https://reference.digilentinc.com/reference/programmable-logic/cmod-s7/start

The HDMI and USB OTG signals do not work correctly on the genesys2 board files.